Capacitor over bitline DRAM cell
AssigneeTexas Instruments Incorporated
InventorsJiann Liu, Clarence W. Teng
Life of this patent
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Abstract
A DRAM array (100) having reduced bitline capacitance. The DRAM cell includes a pass transistor and a storage capacitor (150). An isolation structure (108) surrounds the DRAM cell. The bitline (140) is connected to a source/drain region (120b) of the pass transistor using a first polysilicon plug (112). A second polysilicon plug (110) connects the storage capacitor (150) to the other source/drain region (120a&c) of the pass transistor. Both polysilicon plugs (110, 112) extend through an interlevel dielectric layer (116) to one of the source/drain region (120a-c) of the pass transistor, but neither extends over the isolation structure (108). If desired, either the storage capacitor (150) or the bitline (140) may be offset from the source/drain regions (120a-c).
Claims16
A DRAM cell comprising:
- a moat region;
- an isolating structure surrounding and defining said moat region;
- a pass transistor located in said moat region;
- an interlevel dielectric layer located above said pass transistor and said isolating structure;
- a first and a second doped polysilicon plug each extending through said interlevel dielectric layer to said moat region;
- and
- an offset connecting piece extending from said first doped polysilicon plug to over a portion of said isolating structure, wherein said offset connecting piece is separated from said isolating structure by said interlevel dielectric layer.
A DRAM comprising an array of DRAM cell pairs, each DRAM cell pair comprising:
- a moat region;
- an isolating structure surrounding and defining said moat region;
- a first and a second pass transistor located in said moat region each having a wordline gate and a first source/drain region, wherein said first and second pass transistors share a common second source/drain region;
- an interlevel dielectric layer located above said first and second pass transistors and said isolating structure;
- three polysilicon plugs each extending through said interlevel dielectric layer to one of said first and second source/drain regions;
- and
- a first offset connecting piece extending from one of said three polysilicon plugs to over a portion of said isolating structure, wherein said offset connecting piece extends over said isolating structure and is separated from said isolating structure by said interlevel dielectric layer.
Dependencies are inferred from the claim text.