Low-to-high voltage CMOS driver circuit for driving capacitive loads

A low-to-high voltage CMOS driver circuit for driving a capacitive load, comprising:

• a CMOS output stage having a PMOS transistor and an NMOS transistor coupled between first and second voltage levels, the CMOS output stage providing an output signal that swings between the first and second voltage levels;
• an input stage to receive an input signal that swings between the first voltage level and a third voltage level that is less than the second voltage level, the input stage including a cross-coupled latch generating first and second interdependent control signals based upon the input signal, the first control signal being used to activate one transistor of the CMOS output stage, the input stage further generating a third control signal;
• and
• an intermediate voltage translation stage coupled between the input and output stages, the intermediate voltage translation stage receiving the second control signal from the input stage and using the second control signal to generate an activation signal at the second voltage level, the activation signal activating the other transistor of the CMOS output stage at a different time than the input stage activates the one transistor of the CMOS output stage, the input stage, the output stage, and the intermediate stage operating together to minimize crossing current in the CMOS output stage, the intermediate voltage translation stage including:
• a pair of cross-coupled transistors having inversely related output states;
• first and second control transistors operably respectively controlled by the third and second control signals from the input stage and connected to the pair of cross-coupled transistors to toggle the output states;
• and
• precharge means for precharging the pair of cross-coupled transistors to facilitate transition during toggle between the output states.

A low-to-high voltage CMOS driver circuit for driving a capacitive load, comprising:

• a CMOS output stage having an output, having an NMOS transistor including a gate and a source to drain path coupled between the driver output and a first voltage level, and having a PMOS transistor including a gate and a source to drain path coupled between a second voltage level and the driver output, the second voltage level being higher than the first voltage level, the CMOS output stage providing an output signal that swings between the first and second voltage levels;
• an input stage having a first inverter receiving an input signal that swings between the first voltage level and a third voltage level that is less than the second voltage level, the inverter further including an output, the input stage having a first NOR gate including a first input coupled to the output of the first inverter, including a second input and including an output, the input stage having a second NOR gate including a first input coupled to the output of the first NOR gate, including a second input, and including an output coupled to the gate of the NMOS transistor of the output stage and to the second input of the first NOR gate, and the input stage further having a second inverter including an input coupled to the output of the first inverter and including an output coupled to the second input of the second NOR gate, the output of the second NOR gate defining a first control signal, the output of the first NOR gate defining a second control signal, and the output of the first inverter defining a third control signal;
• and
• an intermediate voltage translation stage coupled between the input stage and the PMOS transistor of the output stage, the voltage translation stage receiving the second control signal from the input stage and using the second control signal to generate an activation signal at the second voltage level, the activation signal activating the PMOS transistor of the output stage at a different time than the input stage activates the NMOS transistor of the CMOS output stage, the intermediate voltage translation stage having a first control transistor including a gate coupled to the output of the first inverter and having a source to drain path between the first voltage level and a first node, the intermediate voltage translation stage further having a second control transistor having a gate coupled to the output of the first NOR gate and having a source to drain path between the first voltage level and a second node, the intermediate voltage translation stage further having a first PMOS transistor having a gate coupled to the second node and having a source to drain path between the second voltage level and the first node, the intermediate voltage translation stage further having a second PMOS transistor having a gate coupled to the first node and having a source to drain path between the second voltage level and the second node, the intermediate translation stage further having a first NMOS precharge transistor including a gate coupled to the output of the first NOR gate and including a source to drain path coupled between the third voltage level and the first node, the intermediate translation stage further having a second NMOS precharge transistor having a gate coupled to the output of the first inverter and having a source to drain path between the third voltage level and the second node, the second node being coupled to the gate of the PMOS transistor of the output stage.

A low-to-high voltage CMOS driver circuit for driving a capacitive load, comprising:

• a CMOS output stage having an output, having an NMOS transistor including a gate and a source to drain path coupled between the driver output and a first voltage level, and having a PMOS transistor including a gate and a source to drain path coupled between a second voltage level and the driver output, the second voltage level being higher than the first voltage level, the CMOS output stage providing an output signal that swings between the first and second voltage levels;
• an input stage having a first and second inverters both receiving an input signal that swings between the first voltage level and a third voltage level that is less than the second voltage level, the first inverter further including an output, the second inverter further including an output, the input stage having a first NAND gate including a first input coupled to the output of the first inverter, including a second input and including an output, the input stage having a second NAND gate including a first input coupled to the output of the first NAND gate, including a second input coupled to the output of the second inverter, and including an output coupled to the second input of the first NAND gate, the input stage further having a third inverter including an input coupled to the output of the first NAND gate and including an output, the input stage further having a fourth inverter including an input coupled to the output of the second NAND gate and including an output coupled to the gate of the NMOS transistor of the output stage;
• and
• an intermediate voltage translation stage coupled between the input stage and the PMOS transistor of the output stage, the intermediate voltage translation stage having a first control transistor including a gate coupled to the output of the first NAND gate and having a source to drain path between the first voltage level and a first node, the intermediate voltage translation stage further having a second control transistor having a gate coupled to the output of the third inverter and having a source to drain path between the first voltage level and a second node, the intermediate voltage translation stage further having a first PMOS transistor having a gate coupled to the second node and having a source to drain path between the second voltage level and the first node, the intermediate voltage translation stage further having a second PMOS transistor having a gate coupled to the first node and having a source to drain path between the second voltage level and the second node.