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US 5,670,821 AGranted
Guard ring for mitigation of parasitic transistors in junction isolated integrated circuits
AssigneeAnalog Devices, Inc.
InventorDerek F. Bowers
Life of this patent
Estimating the term…
Abstract
A guard ring with the same conductivity as a device pocket surrounds the pocket and a pocket isolation ring to establish a parasitic transistor that conducts current between the guard ring and the pocket when the pocket voltage is driven sufficiently below the substrate voltage. The guard ring is connected to a voltage supply for the circuit which, together with its shorter current path, allows the parasitic transistor to harmlessly divert current away from unwanted inter-pocket parasitic transistors.
Claims4
A parasitic protected, junction isolated integrated circuit (IC), comprising:
- a substrate having a doping of one conductivity,
- a first integrated circuit device pocket in said substrate with a doping conductivity opposite to the substrate doping,
- a first active transistor in said device pocket having doped emitter, base and collector regions with respective doping concentrations, a first isolation ring surrounding said pocket,
- a doped guard ring with the same conductivity as said pocket surrounding said isolation ring and, together with said pocket and said substrate, forming a first parasitic transistor, said guard ring having a doping concentration at least about 100 times less than said emitter and collector region doping concentrations, said guard ring having the same type doping conductivity as said active transistor base region, said active transistor base region being integral with said pocket and forming the emitter of said parasitic transistor, and
- a contact for applying a voltage to said guard ring.
2 more elements
Dependencies are inferred from the claim text.