Electrically programmable antifuse

An antifuse and metal interconnect structure in an integrated circuit comprising:

• a substrate having an insulating layer disposed on an upper surface thereof;
• a first multilayer metal interconnect layer disposed on said insulating layer and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode, said first portion including an upper barrier metal layer;
• an antifuse material layer disposed on said lower antifuse electrode;
• an inter-metal dielectric layer disposed on said antifuse material layer and said lower metal interconnect electrode, said inter-metal dielectric layer having an upper antifuse electrode via formed therethrough communicating with said antifuse material and an upper metal interconnect electrode via formed therethrough communicating with said lower metal interconnect electrode;
• and
• a second multilayer metal interconnect layer in said integrated circuit comprising an upper antifuse electrode disposed in said upper antifuse electrode via and on said antifuse material layer and an upper metal interconnect electrode disposed in said upper metal interconnect electrode via and on said lower metal interconnect electrode.

An antifuse and metal interconnect structure in an integrated circuit comprising:

• a substrate having an insulating layer disposed on an upper surface thereof;
• a first multilayer metal interconnect layer disposed on said insulating layer and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode, said first portion including an upper barrier metal layer;
• an inter-metal dielectric layer disposed on said lower antifuse and metal interconnect electrodes, said inter-metal dielectric layer including an antifuse via formed therethrough communicating with said lower antifuse electrode and a metal interconnect via formed therethrough communicating with said lower metal interconnect electrode;
• an antifuse material layer disposed in said antifuse via;
• a barrier layer formed on said antifuse material layer;
• and
• a second multilayer metal interconnect layer in said integrated circuit comprising an upper antifuse electrode disposed on said antifuse material layer and an upper metal interconnect electrode disposed in said upper metal interconnect electrode via and on said lower metal interconnect electrode.

An antifuse and metal interconnect structure in an integrated circuit comprising:

• a substrate having an insulating layer disposed on an upper surface thereof;
• a first multilayer metal interconnect layer disposed on said insulating layer and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode, said first portion including an upper barrier metal layer;
• an antifuse material layer disposed on said lower antifuse electrode;
• a barrier layer formed on said antifuse material layer;
• an inter-metal dielectric layer disposed on said antifuse material layer and said lower metal interconnect electrode, said inter-metal dielectric layer having an upper antifuse electrode via formed therethrough communicating with said antifuse material and an upper metal interconnect electrode via formed therethrough communicating with said lower metal interconnect electrode;
• and
• a second multilayer metal interconnect layer in said integrated circuit comprising an upper antifuse electrode disposed in said upper antifuse electrode via and on said antifuse material layer and an upper metal interconnect electrode disposed in said upper metal interconnect electrode via and on said lower metal interconnect electrode.

An antifuse and metal interconnect structure in an integrated circuit comprising:

• a substrate having an insulating layer disposed on an upper surface thereof;
• a first multilayer metal interconnect layer disposed on said insulating layer and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode, said second portion having a thinner upper layer than said first portion;
• an inter-metal dielectric layer disposed on said lower antifuse and metal interconnect electrodes, said inter-metal dielectric layer including an antifuse via formed therethrough communicating with said lower antifuse electrode and a metal interconnect via formed therethrough communicating with said lower metal interconnect electrode;
• an antifuse material layer disposed in said antifuse via;
• and
• a second multilayer metal interconnect layer in said integrated circuit comprising an upper antifuse electrode disposed on said antifuse material layer and an upper metal interconnect electrode disposed in said upper metal interconnect electrode via and on said lower metal interconnect electrode.

An antifuse and metal interconnect structure in an integrated circuit comprising:

• a substrate having an insulating layer disposed on an upper surface thereof;
• a first multilayer metal interconnect layer disposed on said insulating layer and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode, said second portion having a thinner upper layer than said first portion;
• an antifuse material layer disposed on said lower antifuse electrode;
• an inter-metal dielectric layer disposed on said antifuse material layer and said lower metal interconnect electrode, said inter-metal dielectric layer having an upper antifuse electrode via formed therethrough communicating with said antifuse material and an upper metal interconnect electrode via formed therethrough communicating with said lower metal interconnect electrode;
• and
• a second multilayer metal interconnect layer in said integrated circuit comprising an upper antifuse electrode disposed in said upper antifuse electrode via and on said antifuse material layer and an upper metal interconnect electrode disposed in said upper metal interconnect electrode via and on said lower metal interconnect electrode.

An antifuse and metal interconnect structure in an integrated circuit comprising:

• a substrate having an insulating layer disposed on an upper surface thereof;
• a first multilayer metal interconnect layer disposed on said insulating layer and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode, said second portion having a thinner upper layer than said first portion;
• an inter-metal dielectric layer disposed on said lower antifuse and metal interconnect electrodes, said inter-metal dielectric layer including an antifuse via formed therethrough communicating with said lower antifuse electrode and a metal interconnect via formed therethrough communicating with said lower metal interconnect electrode;
• an antifuse material layer disposed in said antifuse via;
• a barrier layer formed on said antifuse material layer;
• and
• a second multilayer metal interconnect layer in said integrated circuit comprising an upper antifuse electrode disposed on said antifuse material layer and an upper metal interconnect electrode disposed in said upper metal interconnect electrode via and on said lower metal interconnect electrode.

An antifuse and metal interconnect structure in an integrated circuit comprising:

• a substrate having an insulating layer disposed on an upper surface thereof;
• a first multilayer metal interconnect layer disposed on said insulating layer and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode, said second portion having a thinner upper layer than said first portion;
• an antifuse material layer disposed on said lower antifuse electrode;
• a barrier layer formed on said antifuse material layer;
• an inter-metal dielectric layer disposed on said antifuse material layer and said lower metal interconnect electrode, said inter-metal dielectric layer having an upper antifuse electrode via formed therethrough communicating with said antifuse material and an upper metal interconnect electrode via formed therethrough communicating with said lower metal interconnect electrode;
• and
• a second multilayer metal interconnect layer in said integrated circuit comprising an upper antifuse electrode disposed in said upper antifuse electrode via and on said antifuse material layer and an upper metal interconnect electrode disposed in said upper metal interconnect electrode via and on said lower metal interconnect electrode.