Layout for noise reduction on a reference voltage

A layout for reducing power supply noise on a reference voltage, comprising:

• a semiconductive substrate;
• a first conductive layer overlying the semiconductive substrate;
• a second conductive layer overlying the semiconductive substrate, the second conductive layer laterally adjacent to, and spaced apart from, the first conductive layer;
• a first power supply line overlying the first conductive layer and coupled to the first conductive layer;
• a second power supply line overlying the second conductive layer and coupled to the second conductive layer;
• a reference voltage line overlying the first conductive layer and disposed laterally adjacent to the first power supply line for a first predetermined length, the reference voltage line disposed above the second conductive layer and laterally adjacent to the second power supply line for a second predetermined length;
• a third power supply line, coupled to the first power supply line, the third power supply line overlying the first conductive layer and laterally adjacent to the reference voltage line on an opposite side of the first power supply line for the first predetermined length;
• a fourth power supply line, coupled to the first power supply line, the fourth power supply line overlying the second conductive layer and laterally adjacent to the reference voltage line on an opposite side of the second power supply line for the second predetermined length;
• and
• well regions implanted in the semiconductive substrate, the well regions underlying predetermined alternating portions of both of the first and second conductive layers, wherein a capacitive coupling between the first and second conductive layers and the well regions substantially cancels a capacitive coupling between the semiconductive substrate and the first and second conductive layers.