US 5,670,814 A · Electrostatic discharge protection circuit triggered by well-coupling

Abstract

An electrostatic discharge (ESD) protection circuit is disposed between a metal pad and a circuit ground, wherein the pad may be an input pad or an output pad. The circuit includes a thick oxide device, a capacitor, and an NMOS transistor. The thick oxide device is configured with its drain and source connected to the pad and circuit ground, respectively. The gate of the thick oxide device is tied to the pad, and the oxide device bulk is connected to the drain of the NMOS transistor. The NMOS transistor is configured with its source connected to the circuit ground and its gate controlled by a power rail. The capacitor is connected between the pad and the bulk of the thick oxide device. The bulk of the device is constructed by a P-well region formed in a substrate. The capacitor is formed between the pad and a polysilicon layer just therebelow, without consuming extra layout area. When a positive-to-ground ESD pulse is conducted to the pad, the capacitor couples the ESD voltage to the well region and turns on the thick oxide device to bypass the ESD stress. Moreover, a diode is connected between the pad and circuit ground by its cathode and anode, respectively, to bypass a negative-to-ground ESD pulse. The diode can be an extra component or a built-in PN junction. In normal operation, the NMOS transistor is powered on and connects the bulk of the device to the circuit ground without floating of the P-well region.

Claims7

Dependent claims

An electrostatic discharge protection circuit, comprising:

an N-type semiconductor substrate;
a first P-well region and a second P-well region mutually spaced apart and formed in the substrate;
at least one contact region formed in the first P-well region;
an isolating structure formed on the substrate;
a polysilicon layer formed on the isolating structure and coupled to the contact region;
a dielectric layer formed overlying the polysilicon layer;
a metal pad formed on the dielectric layer, wherein the metal pad, the dielectric layer, and the polysilicon layer form a capacitor for coupling ESD stress to the first P-well region when an ESD voltage appears at the pad;
a first heavily-doped N-type region formed in the first P-well region and coupled to the pad;
at least one second heavily-doped N-type region spaced apart from and electrically isolated from the first heavily-doped N-type region, and coupled to a circuit ground, wherein the first heavily-doped N-type region, the second heavily-doped N-type region, and the first P-well region form a bipolar junction transistor which bypasses ESD stress when an ESD voltage is coupled to the first P-well region through the capacitor;
and
an NMOS transistor formed in the second P-well region, the NMOS transistor having a source coupled to the circuit ground, a drain coupled to the contact region, and a gate responsive to a circuit power signal to cause the NMOS transistor to connect the first P-well region to the circuit ground.

8 more elements

Dependencies are inferred from the claim text.

Electrostatic discharge protection circuit triggered by well-coupling

Life of this patent

Electrostatic discharge protection circuit triggered by well-coupling

Life of this patent

Abstract

Claims7