A method of fabricating a semiconductor integrated circuit device having first and second circuit regions provided at first and second surface portions of a semiconductor substrate, said first and second circuit regions being capable of performing first and second functions and including elements having relatively small and large sizes as generally measured in a direction perpendicular to said surface portions of the semiconductor substrate, respectively, an insulating film covering said first and second circuit regions, and wiring conductors provided on said insulating film, the method comprising the steps of:
- preparing a semiconductor substrate having first and second surface portions;
- recessing the second surface portion of said semiconductor substrate;
- forming elements of the first circuit region at a first surface portion of said semiconductor substrate and elements of the second circuit region at said recessed second surface portion of said semiconductor substrate;
- forming an insulating film to cover said first and second circuit regions, with a level difference being caused between first and second portions of said insulating film on said first and second circuit regions, respectively, said second portion of said insulating film being at a higher level than said first portion of said insulating film;
- effecting chemical-mechanical planarization of said insulating film to suppress said level difference in said insulating film for enhancing a focus margin for successive photolithographic steps;
- and
- forming at least one wiring conductor on said insulating film with said suppressed level difference, enjoying said enhanced focus margin.