Dual poly-gate deep submicron CMOS with buried contact technology

A method for manufacturing a CMOS device on a semiconductor substrate, the method comprising:

• forming a first conductivity well and second conductivity well in said substrate;
• forming a gate oxide layer on said substrate;
• forming a first polysilicon layer over said gate oxide layer;
• patterning a first photoresist on said first polysilicon layer;
• etching said gate oxide layer and said first polysilicon layer using said first photoresist as a mask, wherein residual portions of said first polysilicon layer form a gate structure over said first conductivity well and a gate structure over said second conductivity well;
• removing said first photoresist;
• forming polysilicon stack layers on said substrate and said first polysilicon layer;
• patterning a second photoresist on said polysilicon stack layers to define source and drain (S/D) regions and buried contact regions in said first conductivity well;
• etching said polysilicon stack layers and said first polysilicon layer using said second photoresist as a mask to form first trenches in said polysilicon stack layers and said first polysilicon layer, said trenches exposing portions of said substrate and portions of said gate oxide over said first conductivity well;
• doping portions of said substrate aligned with said first trenches to have a second conductivity lightly doped drain (LDD) with halo doping profile;
• forming a first dielectric layer using a liquid phase deposition (LPD) process, wherein said first dielectric layer fills said first trenches in said polysilicon stack layer;
• removing said second photoresist;
• patterning a third photoresist on said polysilicon stack layers to cover said second conductivity well;
• performing a first ion implantation using said third photoresist as a mask to implant ions into portions of said polysilicon stack layers over said first conductivity well;
• stripping said third photoresist;
• patterning a fourth photoresist on said polysilicon stack layers to define S/D regions and buried contact regions in said second conductivity well;
• etching said polysilicon stack layers and said first polysilicon layer by using said fourth photoresist as an etching mask to form second trenches in said polysilicon stack layers and said first polysilicon layer, said second trenches exposing portions of said substrate and portions of said gate oxide over said second conductivity well;
• doping portions of said substrate aligned with said second trenches to have a first conductivity LDD with halo doping profile;
• forming a second dielectric layer using said LPD process, wherein said second dielectric layer fills said second trenches in said polysilicon stack layers;
• stripping said fourth photoresist;
• patterning a fifth photoresist on said polysilicon stack layers to cover said first conductivity well;
• performing an second ion implantation by using said fifth photoresist as a mask to implant ions into portions of said polysilicon stack layers over said second conductivity well;
• stripping said fifth photoresist;
• and
• thermally treating said first and second dielectric layers and said substrate, wherein dopants from said first and second ion implantations diffuse into said substrate to form buried contacts.