Process for self-aligned twin wells without N-well and P-well height difference

A method of forming twin wells without height difference in the fabrication of an integrated circuit device comprising:

• growing a layer of silicon oxide over the surface of a semiconductor substrate;
• depositing a layer of silicon nitride overlying said silicon oxide layer;
• coating a layer of photoresist over said silicon nitride layer;
• exposing said photoresist layer to actinic light and exposing and developing said photoresist layer to form a photoresist mask having an opening to said silicon nitride layer where an N-well is to be formed;
• etching away said exposed silicon nitride layer to expose said underlying silicon oxide layer;
• implanting first ions into said semiconductor substrate through said silicon oxide layer within said opening;
• thereafter removing said photoresist layer;
• depositing a dielectric film over said exposed silicon oxide layer and over said silicon nitride layer;
• etching back said dielectric film with an etch stop at said silicon nitride layer;
• thereafter removing said silicon nitride layer;
• implanting second ions into said semiconductor substrate where it is not covered by said dielectric film;
• thereafter removing said dielectric film;
• and
• driving in said first ions to form said N-well within said semiconductor substrate and driving in said second ions to form a P-well within said semiconductor substrate completing the formation of said twin wells without height difference in the fabrication of said integrated circuit device.

A method of forming twin wells without height difference in the fabrication of an integrated circuit device comprising:

• growing a layer of silicon oxide over the surface of a semiconductor substrate;
• depositing a layer of silicon nitride overlying said silicon oxide layer;
• coating a layer of photoresist over said silicon nitride layer;
• exposing said photoresist layer to actinic light and exposing and developing said photoresist layer to form a photoresist mask having an opening to said silicon nitride layer where an N-well is to be formed;
• etching away said exposed silicon nitride layer to expose said underlying silicon oxide layer;
• implanting first ions into said semiconductor substrate through said silicon oxide layer within said opening;
• thereafter removing said photoresist layer;
• depositing a dielectric film over said exposed silicon oxide layer and over said silicon nitride layer;
• planarizing said dielectric film using chemical mechanical polishing wherein said silicon nitride layer is a stop for said chemical mechanical polishing;
• thereafter removing said silicon nitride layer;
• implanting second ions into said semiconductor substrate where it is not covered by said dielectric film;
• thereafter removing said dielectric film;
• and
• driving in said first ions to form said N-well within said semiconductor substrate and driving in said second ions to form a P-well within said semiconductor substrate completing the formation of said twin wells without height difference in the fabrication of said integrated circuit device.