Locos technology with reduced junction leakage

An integrated circuit device having reduced junction leakage comprising:

• a substrate having a surface;
• field oxide regions formed at the surface of the substrate and extending into the substrate a field oxide depth below the surface of the substrate, the field oxide regions defining an active device region therebetween;
• a MOS transistor formed on the active device region including a gate electrode above the surface of the substrate;
• inner source/drain regions within the substrate adjoining edges of the field oxide regions and extending on either side of the gate electrode to the edges of the field oxide regions;
• outer source/drain regions adjacent the edges of the field oxide regions, the outer source/drain regions extending to an outer source/drain depth deeper than the inner source/drain regions and deeper than the field oxide regions at the edges of the field oxide regions, outer edges of the outer source/drain regions being adjacent the edges of the field oxide regions and wherein inner edges of the outer source/drain regions are spaced from the gate electrode over a middle portion of the gate electrode;
• and
• a contact structure connected to one of the inner source/drain regions between the gate electrode and one of the inner edges of the outer source/drain regions, wherein there is no overlap between the contact region and the outer source/drain region.