Relaxed channel high electron mobility transistor
AssigneeTRW Inc.
InventorsDwight C. Streit, Thomas R. Block
Life of this patent
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Abstract
A pseudomorphic HEMT having a partially relaxed InGaAs channel layer. In order to increase device performance and lower the electron transport energy levels within the potential well defined by the conduction band of the channel layer, the channel layer thickness is increased beyond a critical thickness that defines where a strained InGaAs channel becomes relaxed and forms crystal lattice dislocations. The channel layer is partially relaxed in that the channel layer thickness exceeds the critical thickness, but the thickness of the channel layer is limited so that dislocations only form in a single direction.
Claims15
A semiconductor device including a plurality of semiconductor layers, said device comprising:
- a substrate layer;
- a first semiconductor layer being supported on the substrate layer;
- a second semiconductor layer being supported on the substrate;
- and
- a channel layer being supported on the substrate layer and being positioned between the first and second semiconductor layers, wherein a conduction band of the first and second semiconductor layers and a conduction band of the channel layer define a potential well in the channel layer for electron transport, said channel layer being a partially relaxed channel layer including crystal lattice dislocations formed substantially in a single direction.
A high electron mobility transistor (HEMT) including a plurality of semiconductor layers, said HEMT comprising:
- a substrate layer;
- an AlGaAs buffer layer being supported on the substrate;
- an AlGaAs donor layer being supported on the substrate layer;
- and
- an InGaAs channel layer supported on the substrate layer between the buffer layer and the donor layer, wherein a conduction band of the buffer layer, a conduction band of the donor layer and a conduction band of the channel layer define a potential well in the channel layer for electron transport, said channel layer being a partially relaxed channel layer including crystal lattice dislocations formed substantially in a single direction.
A method of producing a semiconductor device, said method comprising the steps of:
- providing a substrate layer;
- depositing a first semiconductor layer on the substrate in a crystalline format;
- depositing a second semiconductor layer on the substrate layer in a crystalline format;
- and
- depositing a channel layer on the substrate layer between the first and second semiconductor layers in a crystalline format, wherein a conduction band of the first and second semiconductor layers and a conduction band of the channel layer define a potential well in the channel layer for electron transport, said channel layer having crystal lattice dislocations formed substantially in a single direction so as to be a partially relaxed channel layer.
Dependencies are inferred from the claim text.