Method of forming poly plug to reduce buried contact series resistance

A method of fabricating an integrated circuit device having a conduction channel between a source/drain region and an adjoining buried contact junction comprising:

• providing a first layer of polysilicon over a layer of gate silicon oxide over the surface of a semiconductor substrate;
• etching away said first polysilicon and said gate oxide layer where they are not covered by a mask to provide an opening to said semiconductor substrate where planned said buried contact junction will be formed;
• depositing a second polysilicon layer overlying said first polysilicon layer and said planned buried contact junction and doping said second polysilicon layer;
• driving in dopant from said second polysilicon layer to form said buried contact junction;
• depositing a polycide layer overlying said second polysilicon layer;
• etching away said polycide and said second polysilicon layers where they are not covered by a mask to provide a polysilicon contact overlying said buried contact junction and providing an opening to said semiconductor substrate where planned said source/drain region will be formed wherein said planned source/drain region is adjacent to said buried contact junction and wherein a portion of said second polysilicon layer not at said polysilicon contact remains as residue;
• etching away said residue wherein a trench is etched into said semiconductor substrate at the junction of said planned source/drain region and said buried contact junction;
• depositing a doped third polysilicon layer overlying said second polysilicon layer and within said trench;
• etching away said doped third polysilicon layer leaving said doped third polysilicon layer only on the sidewall of said polysilicon contact and within said trench;
• forming a gate electrode overlying said gate silicon oxide layer;
• implanting ions to form said planned source/drain region adjacent to said gate electrode wherein said third polysilicon layer within said trench provides a conduction channel between said source/drain region and said buried contact junction;
• depositing an insulating layer overlying said patterned polycide and second polysilicon layers and said gate electrode;
• and
• depositing a conducting layer through openings in said insulating layer and patterning said conducting layer completing said fabrication of said integrated circuit device.