US 5,668,038 A · One step smooth cylinder surface formation process in stacked cylindrical DRAM products

Abstract

A method of fabrication of a DRAM cell, which forms an improved smooth top cylinder surface and provides controllable cylinder height. A semiconductor structure is provided having a transistor. Also provided are a barrier layer 12 over a first insulating layer 11 on the semiconductor structure. A polysilicon plug 14 extends through the barrier layer 12 and the insulating layer 11. A second insulating layer 16 is formed over portions of the barrier layer 12 and has an opening over the polysilicon plug 14 and over portions of the barrier layer adjacent to the polysilicon plug 14. A polysilicon layer 18 is formed over the second insulating layer 16, the sidewalls of the second insulating layer 16, the portions of the barrier layer 12 adjacent to the polysilicon plug 14 and over the polysilicon plug 14. A gap filling third insulating layer 20 is formed over the polysilicon layer 18. In an important process, potions of the gap filling third insulating layer 20 and the polysilicon layer 18 are etched back in an one step etch process to form a polysilicon cylinder 22. The critical one step etch processes is comprised of two stages: (1) an insulating layer etch stage and (2) a polysilicon etch stage. The second insulating layer 16 and the third insulating layer 20 are then removed thereby formed a stacked polysilicon cylinder.

Claims21

Dependent claims

A method of forming a polysilicon cylinder having a smooth top surface comprising;

a) providing a barrier layer over a first insulating layer on a semiconductor substrate, a polysilicon plug extending through said barrier layer and said insulating layer, a second insulating layer over portions of said barrier layer, said second insulating layer having an opening over said polysilicon plug and over portions of said barrier layer adjacent to said polysilicon plug, said opening defined by sidewalls of said second insulating layer, a polysilicon layer over said second insulating layer, over said sidewalls of said second insulating layer, over said portions of said barrier layer adjacent to said polysilicon plug and over said polysilicon plug, a gap filling third insulating layer over said polysilicon layer;
b) etching back portions of said gap filling third insulating layer and said polysilicon layer in a one step etch process to form a polysilicon cylinder;
said one step etch process comprised of two stages:
(1) an insulating layer etch stage and (2) a polysilicon etch stage, said insulating layer etch stage comprising a plasma enhanced etch using CHF.sub.3, CF.sub.4, and Argon gasses, and said polysilicon etch stage using CF.sub.4, SF.sub.6, and Argon gasses;
and
c) removing said second insulating layer and said gap filling third insulating layer.

3 more elements

A method of forming a polysilicon cylinder having a smooth top surface in a DRAM cell comprising;

a) providing a barrier layer over a first insulating layer on a substrate, said barrier layer composed of silicon nitride, said first insulating layer composed of silicon oxide, a polysilicon plug extending through a plug opening in said barrier layer and said first insulating layer contacting said substrate;
b) forming a second insulating layer composed of silicon oxide over said barrier layer and said polysilicon plug;
c) etching said second insulating layer forming a cylindrical opening over said polysilicon plug and exposing portions of said barrier layer;
said cylindrical opening defined by sidewalls of said second insulating layer;
d) depositing a polysilicon layer over said second insulating layer, over said sidewalls of said second insulating layer, over said polysilicon plug, and over exposed portions of said barrier layer;
e) depositing a gap filling third insulating layer composed of silicon oxide over said polysilicon layer (18);
f) etching back portions of said gap filling third insulating layer and said polysilicon layer in a one step etch process to form a polysilicon cylinder, said one step etch process comprising two stages:
(1) an insulating layer etch stage and (2) a polysilicon etch stage, said insulating layer etch stage comprising a plasma enhanced etch using CHF.sub.3, CF.sub.4, and Argon gasses, said polysilicon etch stage using CF.sub.4, SF.sub.6, and Argon gasses;
and
g) removing said second insulating layer and said gap filling third insulating layer.

7 more elements

Dependencies are inferred from the claim text.

One step smooth cylinder surface formation process in stacked cylindrical DRAM products

Life of this patent

One step smooth cylinder surface formation process in stacked cylindrical DRAM products

Life of this patent

Abstract

Claims21