US 5,668,036 A · Fabrication method of the post structure of the cell for high density DRAM

Abstract

A method is disclosed to form memory cell structures for DRAMs in which the capacitor nodes are formed in the shape of posts that fit in an area no larger than that which is over the active regions of the semiconductor substrate. Hence, the posts are suitable to accommodate the area that is appropriate for any one of the very high density DRAMs up to and including 1 G-bit. Furthermore, one less mask is used to form the node electrode in comparison with prior art. The interior of said post structure constitutes one electrode and the exterior wall the other, while a thin dielectric separates the two polysilicon plates of the capacitor. It is shown that said post structures perform the multi-function of providing a good support during the planarization process. Optional pillars may be formed at judiciously chosen locations in the cell to provide additional storage nodes and/or more uniform support structures to more readily facilitate chemical-mechanical polishing (CMP) of the substrate surface. In an alternate approach for increasing the storage capacity of capacitors in DRAMs, a branched-post structure is used. It is predicted that cells with four branches can allow the manufacture of 1 G-bit DRAMs.

Claims43

Dependent claims

A method of forming multipurpose unitary post structures as storage nodes in dynamic random access memory (DRAM) cells comprising the steps of:

providing a semiconductor substrate over which are formed first polysilicon I gates on gate oxide;
depositing over said substrate a layer of silicon nitride (SIN);
depositing over said SiN a first layer of dielectric;
planarizing said first dielectric layer;
forming a mask over said first dielectric layer;
opening first set of contact holes through said first dielectric layer;
forming said storage node openings in said first dielectric layer for said unitary post structures;
etching native oxide formed in said contact holes;
depositing second polysilicon II over said substrate;
etching back said polysilicon II layer;
removing said first dielectric layer to form said unitary post structures;
removing said silicon nitride layer;
depositing dielectric film over said substrate;
depositing third polysilicon III layer over said dielectric film;
etching said polysilicon III layer to form outer node electrode;
depositing second dielectric layer over said substrate;
planarizing said second dielectric layer;
opening second set of contact holes through said second dielectric layer;
opening contact holes on the periphery of chip sites;
depositing fourth polysilicon IV over said substrate;
etching back said polysilicon IV layer;
depositing third dielectric layer over said substrate;
planarizing said third dielectric layer;
opening third set of contact holes through said third dielectric layer;
depositing metal layer over said substrate;
etching said metal layer to form patterns;
and
depositing a passivation layer over said substrate.

25 more elements

Dependencies are inferred from the claim text.

Fabrication method of the post structure of the cell for high density DRAM

Life of this patent

Fabrication method of the post structure of the cell for high density DRAM

Life of this patent

Abstract

Claims43