Post passivation programmed mask ROM

An array of read only memory cells, comprising:

• a semiconductor substrate doped to a first conductivity type having a surface;
• a layer of insulating material on the surface of the semiconductor substrate;
• first, second and third gate electrodes spaced laterally over the layer of insulating material, each of the gate electrodes having an upper gate electrode surface;
• a first insulating glass layer over each of the upper gate electrode surfaces and over the layer of insulating material between the first and second and between the second and third gate electrodes;
• second doped insulating glass layers on the first insulating glass layer between the first and second gate electrodes and between the second and third gate electrodes, the second doped insulating glass layers extending below the upper gate electrode surfaces and localized so that the second doped glass layers do not extend over the first, second and third gate electrodes,
• the first insulating glass layer and the second doped insulating glass layers providing a planarized surface above the upper gate electrode surfaces;
• and
• a passivation layer over the planarized surface.