US 5,665,994 AGranted

Integrated device with a bipolar transistor and a MOSFET transistor in an emitter switching configuration

AssigneeCo.Ri.M.Me-Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

InventorSergio Palara

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Abstract

A device integrated on a chip of a semiconductor material is disclosed which comprises an NPN bipolar transistor and an N-channel MOSFET transistor in an emitter switching configuration, both being vertical conduction types. The bipolar transistor has its base and emitter regions buried; the MOSFET transistor is formed with an N region bounded by the base and the emitter regions and isolated by a deep base contact and isolation region. To improve the device performance, especially at large currents, an N+ region is provided which extends from the front of the chip inwards of the isolated region and around the MOSFET transistor. In one embodiment of the invention, a MOSFET drive transistor is integrated which has its drain terminal in common with the collector of the bipolar transistor, its source terminal connected to the base of the bipolar transistor, and its gate electrode connected to the gate electrode of the MOSFET transistor in the emitter switching configuration.

Claims20

Dependent claims

A device comprising at least a pair of transistors, namely a bipolar one and a MOSFET one, connected into an emitter switching configuration and integrated on a semiconductor material, which device comprises:

a substrate of the N type having a first surface, a second opposite surface, and a high concentration of impurities;
at least one layer of the N type overlying the first surface of the substrate and having a lower concentration of impurities than the substrate, such layer and substrate including the collector region of the bipolar transistor;
a metallic layer which extends across the second opposite surface of the substrate from the at least one layer and constitutes the collector terminal of the bipolar transistor;
a region of the P type having a low concentration of impurities which is buried in the N-type layer and includes the base region of the bipolar transistor;
an isolation region of the P type having a high concentration of impurities and extending from a front surface of the at least one layer overlying the substrate, as far as the edge of the base region, thereby bounding inwardly an isolated region of the N type which includes the drain region of the MOSFET transistor;
electrically conductive means of contact on said isolation region which include the base terminal of the bipolar transistor;
a buried region of the N type having a high concentration of impurities which forms a junction with the base region and includes the emitter region of the bipolar transistor;
a region of the P type which extends from the front surface of the at least one layer overlying the substrate inwards of the isolated region and includes the channel of the MOSFET transistor;
a region of the N type having a high concentration of impurities which extends from the front surface of the at least one layer overlying the substrate in said region of the P type including the channel of the MOSFET transistor and includes the source region of the MOSFET transistor;
electrically conductive means of contact on said source region which include the source terminal of the MOSFET transistor;
a strip of an electrically conductive material overlying the channel, being insulated from the front surface of the at least one layer overlying the substrate by a layer of an insulating material, and including the gate electrode of the MOSFET transistor;
and
an additional region of the N type having a high concentration of impurities and extending from the front surface of the at least one layer overlying the substrate inwards of the isolated region of the N type and surrounding the region of the P type which includes the channel.

10 more elements

A device having a bipolar transistor and a MOSFET transistor coupled in an emitter switching configuration, comprising:

an N substrate that has front and back surfaces and a first impurity concentration;
an N layer that adjoins said front surface of said substrate and has a second impurity concentration that is lower than said first;
wherein said substrate and said layer include a collector region of said bipolar transistor;
a metallic layer that adjoins said back surface of said substrate and forms a collector terminal of said bipolar transistor;
a buried P region that is buried in said N layer, includes a base region of said bipolar transistor, and has a third concentration of impurities;
a P isolation region that extends outwardly from said buried P region opposite said substrate and has a fourth impurity concentration that is higher than said third;
a bounded N region that is bounded by said P isolation region and includes a drain region of said MOSFET transistor;
a first contact that adjoins said P isolation region and forms a base terminal of said bipolar transistor;
a buried N region that forms a junction with said base region, includes an emitter region of said bipolar transistor, and has a fifth impurity concentration that is higher than said second;
an N isolation region that is within and bounds a portion of said bounded N region and has a sixth impurity concentration that is higher than said second;
a P region that is within said portion and includes a channel of said MOSFET transistor;
an N region that is within said P region, includes a source region of said MOSFET transistor, and has a seventh impurity concentration that is higher than said second;
a second contact that adjoins said N region and forms a source terminal of said MOSFET transistor;
a third contact that overlies said channel and forms a gate electrode of said MOSFET transistor;
and
an insulator layer that separates said third contact from said channel.

13 more elements

A semiconductor device having a bipolar transistor and a MOSFET switching transistor coupled in an emitter switching configuration and a MOSFET drive transistor and said bipolar transistor coupled in a Darlington configuration, the device comprising:

an N substrate that has front and back surfaces and a first impurity concentration;
an N layer that adjoins said front surface of said substrate and has a second impurity concentration that is lower than said first;
wherein said substrate and said layer include a collector region of said bipolar transistor;
a metallic layer that adjoins said back surface of said substrate and forms a collector terminal of said bipolar transistor;
a P region that is buried in said N layer, includes a base region of said bipolar transistor, and has a third concentration of impurities;
a P isolation region that extends outwardly from said buried P region opposite said substrate and has a fourth impurity concentration that is higher than said third;
a bounded N region that is bounded by said P isolation region and includes a drain region of said MOSFET switching transistor;
a first contact that adjoins said P isolation region and forms a base terminal of said bipolar transistor;
a buried N region that forms a junction with said base region, includes an emitter region of said bipolar transistor, and has a fifth impurity concentration that is higher than said second;
an N isolation region that is within and bounds a portion of said bounded N region and has a sixth impurity concentration that is higher than said second;
a P region that is within said portion and includes a channel of said MOSFET switching transistor;
a first N region that is within said P region, includes a source region of said MOSFET switching transistor, and has a seventh impurity concentration that is higher than said second;
a second contact that adjoins said first N region and forms a source terminal of said MOSFET switching transistor;
a third contact that overlies said channel and forms a gate electrode of said MOSFET switching transistor;
a first insulator layer that separates said third contact from said channel;
an outward P region that is within the N layer, adjacent to an outer edge of said P isolation region, and includes a channel of said MOSFET drive transistor;
a second N region that is within said outward P region, includes a source region of said MOSFET drive transistor, and has an eighth impurity concentration that is higher than said second;
a fourth contact that overlies said channel of said MOSFET drive transistor and includes a gate electrode thereof;
a second insulator layer that separates said fourth contact from said channel of said MOSFET drive transistor;
and
wherein a portion of said N layer that is bounded by said outward P region and said substrate forms with said substrate a drain region of said MOSFET drive transistor.

18 more elements

A semiconductor device comprising:

first and second stages each including a bipolar transistor and a MOSFET switching transistor coupled in an emitter switching configuration, each of said stages comprising:
an N substrate that has front and back surfaces and a first impurity concentration;
an N layer that adjoins said front surface of said substrate and has a second impurity concentration that is lower than said first;
wherein said substrate and said layer include a collector region of said bipolar transistor;
a metallic layer that adjoins said back surface of said substrate and forms a collector terminal of said bipolar transistor;
a buried P region that is buried in said N layer, includes a base region of said bipolar transistor, and has a third concentration of impurities;
a P isolation region that extends outwardly from said buried P region opposite said substrate and has a fourth impurity concentration that is higher than said third;
a bounded N region that is bounded by said P isolation region and includes a drain region of said MOSFET switching transistor;
a first contact that adjoins said P isolation region and forms a base terminal of said bipolar transistor;
a buried N region that forms a junction with said base region, includes an emitter region of said bipolar transistor, and has a fifth impurity concentration that is higher than said second;
an N isolation region that is within and bounds a portion of said bounded N region and has a sixth impurity concentration that is higher than said second;
a P region that is within said portion and includes a channel of said MOSFET switching transistor;
a first N region that is within said P region, includes a source region of said MOSFET switching transistor, and has a seventh impurity concentration that is higher than said second;
a second contact that adjoins said first N region and forms a source terminal of said MOSFET switching transistor;
a third contact that overlies said channel and forms a gate electrode of said MOSFET switching transistor;
and
a first insulator layer that separates said third contact from said channel;
and
a MOSFET drive transistor coupled in a Darlington configuration with the bipolar transistor of said first stage, said drive transistor comprising:
a P outward region that is within said N layer, is adjacent to an outer edge of said P isolation region of said bipolar transistor in said first stage, and includes a channel of said MOSFET drive transistor;
a second N region that is within said P outward region, includes a source region of said MOSFET drive transistor, and has a ninth impurity concentration that is greater than said second;
a fourth contact that overlies said channel of said MOSFET drive transistor and includes a gate electrode thereof;
a second insulator layer that separates said fourth contact from said channel of said MOSFET drive transistor;
and
wherein a portion of said N layer that is bounded by said P outward region and said substrate forms with said substrate a drain region of said MOSFET drive transistor.

22 more elements

Dependencies are inferred from the claim text.