Silicon etching method
AssigneeInternational Business Machines Corporation
InventorsYoung Hoon Lee, Keith Raymond Milkove, John William Stiebritz, Jr.
Life of this patent
Estimating the term…
Abstract
A method for etching silicon is described incorporating first and second steps of reactive ion etching through a patterned oxide layer in respective atmospheres of HBr, Cl.sub.2 and O.sub.2 and then HBr and O.sub.2 in situ by terminating the first etching step and removing substantially all Cl.sub.2 before continuing with the second step of etching. The invention overcomes the problem of uneven etching of n+ and p+ silicon gates for CMOS transistor logic during the step of simultaneously etching silicon to form sub 0.25 micron gate lengths and vertical sidewalls while stopping on the gate oxide.
Claims16
A method for forming vertical sidewalls from a silicon layer situated on top of a dielectric layer, comprising the steps of:
- providing a patterned oxide layer on top of said silicon layer protecting the areas which are not to be etched during a subsequent etch step, and leaving other areas thereof exposed,
- first reactive ion etching the exposed areas of the silicon layer through the patterned oxide layer at a pressure of less than 50 mTorr in an atmosphere of HBr, Cl.sub.2, and O.sub.2 whereby sidewalls of the patterned silicon layer are oxidized during said step,
- terminating said step of first reactive ion etching of said silicon layer a predetermined distance above said dielectric layer,
- removing substantially all Cl.sub.2 from said atmosphere, and
- second reactive ion etching the exposed areas of the silicon layer through said patterned oxide layer down to said dielectric layer at a pressure below 50 mTorr.
Dependencies are inferred from the claim text.