Multi-step planarization process using polishing at two different pad pressures

A process for fabricating a semiconductor device comprising the steps of:

• providing a semiconductor substrate having a plurality of elevated regions and a plurality of recessed regions therein,
• wherein a portion of the recessed regions are characterized by a first horizontal distance, and
• wherein a portion of the recessed regions are characterized by a second horizontal distance, and
• wherein the second horizontal distance is different from the first horizontal distance, and
• wherein a first planarization layer overlies the elevated regions;
• depositing a fill material to overlie the first planarization layer and the plurality of recessed regions;
• forming a second planarization layer to overlie the fill material wherein the second planarization material is not lithographically patterned to expose any portion of the underlying fill material;
• chemical-mechanical-polishing a first portion of the fill material using a polishing apparatus having a polishing pad, wherein the first portion is planarized at a first pad pressure;
• and
• chemical-mechanical-polishing a second portion of the fill material at a second pad pressure,
• wherein the first pad pressure is greater than the second pad pressure.

A process for fabricating a semiconductor device comprising the steps of:

• providing a substrate having elevated regions vertically separated from recessed regions by a separation distance;
• forming a first planarization layer overlying the elevated regions;
• depositing a fill material on the substrate to a thickness greater than the separation distance;
• forming a second planarization layer to overlie the fill material;
• removing a first portion of the fill material and a first portion of the second planarization layer, and leaving a second portion of the fill material and a second portion of the second planarization layer, the step of removing being performed by polishing the wafer during a first time period at a first polishing pad pressure and polishing the wafer during a second time period at a second polishing pad pressure wherein the second time period follows the first time period and wherein the second polishing pad pressure is less than the first polishing pad pressure;
• etching the second portion of the fill material using the second portion of the second planarization layer as an etch mask;
• and
• removing the second portion of the second planarization layer whereby the second portion of the fill material remains overlying the recessed regions.

A process for fabricating a semiconductor device comprising the steps of:

• providing a semiconductor substrate having elevated regions and recessed regions therein, wherein a first planarization layer overlies the elevated regions;
• depositing a fill material to overlie the first planarization layer and the recessed regions;
• forming a second planarization layer to overlie the fill material;
• providing a chemical-mechanical-polishing apparatus having a polishing pad and means for variably applying a contact pressure between the polishing pad and the semiconductor substrate;
• polishing a first portion of the fill material, wherein the first portion is polished at a first contact pressure wherein the first contact pressure is created by the means for variably applying a contact pressure so that a polishing selectivity ratio between the fill material and the second planarization layer is N:1, N being a finite positive number;
• and
• polishing a second portion of the fill material at a second contact pressure wherein the second contact pressure is created by the means for variably applying a contact pressure so that a polishing selectivity ratio between the fill material and the second planarization layer is M:1, M being a finite positive number,
• wherein the first contact pressure is greater than the second contact pressure and wherein M is greater than N.