US 5,665,199 AGranted

Methodology for developing product-specific interlayer dielectric polish processes

AssigneeAdvanced Micro Devices, Inc.

InventorsKashmir S. Sahota, Steven C. Avanzino

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Abstract

A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer for a specific product or a specific patterned metal layer is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer. The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size. This polish process development methodology can also be applied to products requiring multiple planarizations for multiple levels of interconnects.

Claims24

Dependent claims

A method for characterizing polishing of semiconductor product wafers comprising a film coating having a film coating thickness deposited over patterned features on an underlayer, said polishing being used to remove steps in said film coating caused by said patterned features, said semiconductor product wafers comprising a plurality of identical die sites across said semiconductor product wafer, said method comprising:

(a) polishing a first patterned test wafer selected from said semiconductor product wafers for a time long enough to remove an amount of film coating equal to the step height of said patterned features;
(b) determining four locations within a single die on said first patterned test wafer corresponding to (i) a location at or near the location of maximum removal of said film coating, (ii) a location at or near the location of minimum removal of said film coating, (iii) a first position over a measurable topographic feature and (iv) a second position adjacent said first position in a region not over said patterned features;
(c) measuring said film coating thickness at said four locations on said first patterned test wafer;
(d) determining the highest point on said film coating within said single die;
(e) measuring the difference between said film coating thickness at said highest point and said location at or near said location of minimum removal;
(f) adding said difference in said film coating thickness between said highest point and said location at or near said location of minimum removal to the difference between said film coating thickness at said location at or near said location of minimum removal and said location at or near said location of maximum removal to calculate a total indicated range;
(g) determining the total indicated range variation;
(h) calculating the maximum step height for a worst case step in said film coating;
(i) selecting at least one additional patterned test wafer from said semiconductor product wafers;
(j) selecting a removal target for each of said additional patterned test wafers such that said maximum step height for said worst case step in said film coating is maintained below a designated step height;
(k) measuring said film coating thickness of each of said additional patterned test wafers at said four locations;
(l) polishing each of said additional patterned test wafers for a time long enough to remove an amount of film coating equal to each of said removal targets;
(m) measuring said film coating thickness at said four locations on each of said additional patterned test wafers;
(n) determining said total indicated range and said total indicated range variation for each of said additional patterned test wafers;
(o) visually inspecting each of said additional patterned test wafers for steps in said film coating;
and
(p) choosing an optimum removal target for processing said semiconductor product wafers.

14 more elements

A method for characterizing and developing a polish process for polishing a lot of semiconductor product wafers comprising an interlayer dielectric layer having an interlayer dielectric thickness deposited over patterned features and field oxide in field areas between said patterned features, said polishing being used to remove steps in said interlayer dielectric layer, said steps caused by said patterned features, steps in an underlayer or different structures all which lie beneath said interlayer dielectric layer, said semiconductor product wafers comprising a plurality of identical die sites across said semiconductor product wafer, said method comprising:

(a) choosing a first patterned test wafer from said lot of semiconductor product wafers;
(b) measuring said interlayer dielectric thickness at a first position over a measurable topographic feature and at a second position in a field area adjacent said position;
(c) providing a plurality of blank test wafers each comprising an interlayer dielectric formed on a blank semiconductor substrate comprising the same composition, and thickness as said interlayer dielectric layer formed on said semiconductor product wafers;
(d) polishing said first patterned test wafer and a first blank test wafer selected from said plurality of blank test wafers to remove an amount of interlayer dielectric equal to the height of said patterned features;
(e) determining four locations within a single die on said first patterned test wafer corresponding to (i) the location of maximum removal of said interlayer dielectric layer over said field areas, (ii) the location of minimum removal of said interlayer dielectric layer over said field areas, (iii) said first position over said measurable topographic features and (iv) said second position in said field area adjacent said first position;
(f) measuring said interlayer dielectric thickness of said first patterned test wafer at said four locations;
(g) determining the highest point on said interlayer dielectric layer within said single die;
(h) measuring the difference between said interlayer dielectric thickness at said highest point and said location of minimum removal;
(i) adding said difference in said interlayer dielectric thickness between said highest point and said location of minimum removal to the difference between the interlayer dielectric thickness at said location of minimum removal and said location of maximum removal to calculate a total indicated range;
(j) determining said highest point on said interlayer dielectric layer within at least one other die site and repeating steps (h) and (i) to calculate an average total indicated range and a total indicated range variation;
(k) calculating the maximum step height for a worst case step in said interlayer dielectric layer;
(l) choosing at least one additional patterned test wafer from said lot of product wafers and at least one additional blank test wafer from said plurality of blank test wafers;
(m) selecting a removal target for each of said additional patterned test wafers and each of said additional blank test wafers such that the maximum step height for a worst case step in said interlayer dielectric layer is maintained below a designated step height;
(n) measuring said interlayer dielectric thickness of each of said additional patterned test wafer at said four locations;
(o) polishing each of said additional patterned test wafers and each of said additional blank test wafers to remove an amount of interlayer dielectric equal to each of said removal targets;
(p) re-measuring said interlayer dielectric thickness at said four locations on each of said additional patterned test wafers;
(q) determining said average total indicated range and said total indicated range variation for each of said additional patterned test wafers by repeating steps (g), (h) and (i);
(r) inspecting each of said additional patterned test wafers for steps on said interlayer dielectric layer;
and
(s) choosing an optimum removal target for processing said semiconductor product wafers remaining in said lot based on said interlayer dielectric thickness measured at said four locations, said average total indicated range and said total indicated range variation for said additional patterned test wafers, and information obtained from inspecting each of said additional patterned test wafers.

17 more elements

Dependencies are inferred from the claim text.