Low inductance termination resistor arrays
AssigneeSun Microsystems, Inc.
InventorHoward L. Davidson
Life of this patent
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AssigneeSun Microsystems, Inc.
InventorHoward L. Davidson
Estimating the term…
An array of termination resistors has symmetrical geometry producing essentially no net magnetic field and a resultant low inductance is fabricated on a substrate as disk resistors. Conductive through vias are formed in the substrate in an array pattern defining what will be resistor first and second contacts. Each disk resistor has one first contact located at the resistor disk center, and preferably four second contacts located symmetrically about the resistor disk and shared by four adjacent disk resistors. For each resistor, a annular-shaped disk of resistive material is fabricated on a first surface of the substrate, such that a central opening in the disk overlies at least the upper surface of a first contact via. The disk geometry and material determines its resistance. Next, a layer of conductive material is formed over the first surface of the substrate to cover at least the periphery of each disk, and to fill the central opening in each disk. This conductive material electrically couples at least the periphery of each resistive disk with each second contact via to define V.sub.T nodes, and also separately electrically couples the disk center to the underlying first contact via. Solder balls at the lower surface of each via provide an array of first and second contacts for each resistor for attaching the substrate to a printed wiring board or other substrate. An array may include hundreds of termination resistors having substantially real impedances in the range of 50 .OMEGA. to 100 .OMEGA. at frequencies up to about 12 GHz.
A method of forming planar array of value-trimmable termination resistors having reduced parasitic impedance, the method comprising:
A method for forming a planar array of N termination resistors each having a first contact and at least M second contacts where M>N wherein one of said second contacts can be a second contact for more than one of said resistors, the method comprising the following steps:
A planar of N termination resistors each resistor having a first contact and at least M second contacts where M>N and where one of said second contacts can be a second contact for more than one said resistors, the array comprising:
Dependencies are inferred from the claim text.