Intelligent test line system
AssigneeKabushiki Kaisha Toshiba
InventorMitsugi Ogura
Life of this patent
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Abstract
Process information obtained by a process section is input to a host computer. The process information includes information about a film, information about etching, information about cleaning, information about heat treatment, and information about a test. Yield information obtained by a D/S section is also input to the host computer. The host computer classifies wafers or lots into a plurality of quality ranks on the basis of these pieces of information, and supplies process conditions determined on the basis of the quality ranks to a burn-in section and a test section. The burn-in section and the test section respectively execute screening tests on the basis of the process conditions.
Claims3
An intelligent test line system comprising:
- means for processing a semiconductor wafer;
- first classifying means for classifying the semiconductor wafer on the basis of information obtained by said processing means into a first quality rank;
- means for determining a stress rank of the semiconductor circuits of the semiconductor wafer in accordance with said first quality rank;
- means for applying to the semiconductor circuits of the semiconductor wafer a stress test based upon said determined stress rank;
- means for evaluating a plurality of semiconductor circuits on the semiconductor wafer;
- and
- second classifying means for classifying the semiconductor circuits on the basis of information obtained by said evaluating means into a second quality rank.
Dependencies are inferred from the claim text.