US 5,635,415 A · Method of manufacturing buried bit line flash EEPROM memory cell

Abstract

A MOSFET device and a method of fabricating an MOSFET device on a lightly doped semiconductor substrate are described. First, form buried bitlines in the substrate. Form conductive, complementary bitline structures formed of doped polycrystalline silicon, the structures having lower surfaces formed on the buried bitlines in electrical contact therewith, and the complementary bitline structures having top surfaces and sidewalls. Form a polysilicon oxide of the doped polycrystalline silicon from the complementary bitline structures over the top surfaces thereof. Oxidize to form tunneling oxide polysilicon oxide sidewall layers adjacent to the complementary bitline structures. Simultaneously, form a tunnel oxide layer over the substrate between the complementary bitline structures. Form floating gates over the tunnel oxide layer and between the sidewall layers. Form an interconductor dielectric layer over the device Finally, form an array of wordlines over the interconductor dielectric layer.

Claims22

Dependent claims

A method of fabricating a non-volatile memory device on a semiconductor substrate comprises:

forming buried bitlines in said substrate;
forming conductive, complementary bitline structures of doped polycrystalline silicon on said buried bitlines and in electrical contact therewith, said complementary bitline structures having top surfaces and sidewalls;
forming protective insulating layers on said top surfaces of said complementary bitline structures;
forming tunneling oxide sidewall layers adjacent to said complementary bitline structures and forming a tunnel oxide layer over said substrate between said complementary bitline structures;
depositing a floating gate polysilicon layer over said protective insulating layers, said tunneling oxide sidewall layers and said tunnel oxide layer;
removing portions of said floating gate polysilicon layer to define floating gates having top surfaces level with upper surfaces of said protective insulating layer;
forming an interconductor dielectric layer over said device;
and
forming an array of wordlines over said interconductor dielectric layer.

6 more elements

A method of fabricating a non-volatile device on a lightly doped semiconductor substrate comprising:

forming a first dielectric layer on said substrate;
forming a patterning layer over said dielectric layer;
patterning said patterning layer by forming a mask with a pattern over said pattering layer and etching the pattern in said mask into said patterning layer;
ion implanting dopant into buried N+ source/drain regions in said substrate exposed by said mask;
forming a blanket doped polysilicon 1 layer over said device;
planarizing said polysilicon 1 layer down to said patterning layer, exposing the surface of said polysilicon 1 layer and forming a bitline layer;
forming a first polysilicon oxide layer on said exposed surface of said polysilicon 1 layer;
removing the remainder of said patterning layer after said patterning step;
etching away said first dielectric layer down to said substrate;
oxidizing sidewalls of said polysilicon 1 layer to form a tunneling oxide sidewall layer from said polysilicon 1 layer, and oxidizing the exposed surface of said substrate to form a tunnel oxide layer thereon;
forming a blanket doped polysilicon 2 layer over said device;
planarizing said polysilicon 2 layer down to said first polysilicon oxide over the surface of said polysilicon 1 layer to form floating gate structures from said polysilicon 2 layer;
forming a blanket dielectric layer over said floating gate device;
forming a blanket polysilicon 3 layer over said blanket dielectric layer;
forming a control gate mask on said device;
patterning said polysilicon 3 layer by etching portions of said polysilicon 3 layer unprotected by said control gate mask;
and
removing said control gate mask.

15 more elements

Dependencies are inferred from the claim text.

Method of manufacturing buried bit line flash EEPROM memory cell

Life of this patent

Method of manufacturing buried bit line flash EEPROM memory cell

Life of this patent

Abstract

Claims22