Process for fabricating a non-volatile memory cell in a semiconductor device

A process for fabricating a non-volatile memory cell in a semiconductor device comprising the steps of:

• provide a semiconductor substrate having an active region therein bounded by a field isolation region, the active region including a programming region and an erasing region,
• wherein the programming region resides at a first portion of the active region and the erasing region resides at a second portion of the active region:
• forming a tunnel dielectric layer overlying the active region:
• forming a floating gate electrode of a first conductivity type overlying the programming region and the erasing region,
• wherein the floating gate electrode is separated from each region by the tunnel dielectric layer;
• forming a masking layer overlying the semiconductor substrate, the masking layer having an opening therein exposing the erasing region;
• implanting dopant atoms through the floating gate electrode and the tunnel dielectric layer and into the erasing region using the masking layer as a doping mask to form a continuous doped region underlying the floating gate electrode:
• and
• forming a control gate electrode overlying the floating gate electrode said separated therefrom by a dielectric layer.

A process for fabricating a non-volatile memory cell in a semiconductor device comprising the steps of:

• providing a semiconductor substrate of a first conductivity type;
• forming a dielectric layer overlying the semiconductor substrate, the dielectric layer having a thickness sufficient to allow transportation of electrical charge therethrough;
• forming a gate electrode overlying the dielectric layer;
• introducing dopant atoms of a second conductivity type into the semiconductor substrate on either side of the gate electrode to form two separate doped regions;
• and
• applying thermal energy to the semiconductor substrate to laterally diffuse the dopant atoms from each doped region, such that a continuous doped region is formed underlying the gate electrode.

A process for fabricating a non-volatile memory cell in a semiconductor device comprising the steps of:

• providing a semiconductor substrate of a first conductivity type having an active region therein bounded by an isolation region;
• forming a first dielectric layer overlying the active region;
• forming an opening in the first dielectric layer exposing a portion of the active region;
• forming a second dielectric layer overlying in the exposed portion of the active region, the second dielectric layer having a thickness sufficient to allow transportation of electrical charge therethrough;
• forming a floating gate electrode of a second conductivity type overlying the isolation region and the second dielectric layer;
• introducing dopant atoms of the second conductivity type into the active region on either side of the floating gate electrode to form two separate doped regions;
• and
• applying thermal energy to the semiconductor substrate to laterally diffuse the dopant atoms from each doped region, such that a continuous doped region is formed underlying the floating gate electrode.