US 5,633,181 AGranted

Fabrication method of semiconductor integrated circuit device having capacitors, bipolar transistors and igfets

AssigneeNEC Corporation

InventorShigeru Hayashi

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Abstract

A fabrication method that enables to realize a semiconductor integrated circuit device having capacitors, bipolar transistors and IGFETs at a lower fabrication cost and a higher fabrication yield than the case of the conventional ones. After a first patterned conductor film having contours of first capacitor electrodes and of base electrodes is formed, a first patterned insulator film is formed on the first capacitor electrodes to produce first dielectrics A second patterned conductor film having contours of second capacitor electrodes and of gate electrodes is then formed on the first capacitor electrodes and the gate insulators. A second patterned insulator film is formed on the second capacitor electrodes to produce second dielectrics. A third patterned conductor film having contours of third capacitor electrodes and of emitter electrodes is formed on the second dielectrics, the base regions and source/drain regions. Each capacitor has a multi-layer structure of the first capacitor electrode, the first dielectric, the second capacitor electrode the second dielectric, and the third capacitor electrode. Each bipolar transistor has the base electrode contacted with the base region and the emitter electrode contacted with the emitter region.

Claims11

Dependent claims

In a fabrication method of a semiconductor device containing capacitors, bipolar transistors and IGFETs on or over a semiconductor substrate, said capacitors being placed in capacitor areas, said bipolar transistors being placed in bipolar transistor areas, and said IGFETs being placed in IGFET areas;

each of said capacitors having a multi-layer structure of a first capacitor electrode located at a nearest level to said substrate, a first dielectric formed on said first capacitor electrode, a second capacitor electrode formed on said first dielectric, a second dielectric formed on said second capacitor electrode, and a third capacitor electrode formed on said second dielectric;
each of said bipolar transistors having a base electrode contacted with a base region formed in said substrate, and an emitter electrode contacted with an emitter region formed in said substrate;
each of said IGFETs having a gate insulator film formed on said substrate, and a gate electrode formed on said gate insulator film;
said method comprising the steps of:
(a) forming a first patterned conductor film to be contacted with said substrate in said bipolar transistor areas, said first conductor film having contours of said first capacitor electrodes in said capacitor areas and contours of said base electrodes in said bipolar transistor areas;
(b) forming a first patterned insulator film on said first capacitor electrodes to produce said first dielectric;
(c) forming a second patterned conductor film on said first capacitor electrodes and a gate insulator film formed on said substrate in said IGFET areas, said second conductor film having contours of said second capacitor electrodes in said capacitor areas and contours of aid gate electrodes in said IGFET areas;
(d) forming a second patterned insulator film on said second capacitor electrodes to produce said second dielectric;
(e) forming a third patterned conductor film on said second dielectric, said base regions and source/drain regions formed in said substrate in said IGFET areas, said third conductor film having contours of said third capacitor electrodes in said capacitor areas and contours of said emitter electrodes in said bipolar transistor areas.

6 more elements

A fabrication method of a semiconductor integrated circuit device having capacitors, bipolar transistors and IGFETs on or over a semiconductor substrate, said capacitors being placed in capacitor areas, said bipolar transistors being placed in bipolar transistor areas, and said IGFETs being placed in IGFET areas;

said method comprising the steps of:
(a) preparing a semiconductor substrate having an isolation insulator film selectively formed therein to define first active regions for bipolar transistors and second active regions for IGFETs;
each of said first active regions containing a collector region and a base region;
(b) forming a first conductor film on said isolation insulator film over said entire substrate, said first conductor film being contacted with said first active regions and covering said second active regions;
(c) forming a first insulator film on said first conductor film over said entire substrate;
(d) forming a first patterned mask on said first insulator film;
(d) patterning said first insulator film and said first conductor film using said first mask to produce first capacitor electrodes and first dielectrics in said capacitor areas and to have contours of base electrodes in said bipolar transistor areas;
said first insulator film and said first conductor film being removed to expose said second active regions in said IGFET areas;
(e) forming gate insulator films on said exposed second active regions, respectively;
(f) forming a second conductor film over said entire substrate, said second conductor film covering said first capacitor electrodes and said first dielectrics in said capacitor areas, said patterned first insulator film and said patterned first conductor film in said bipolar transistor areas, and said gate insulator film in said IGFET areas;
(g) forming a second insulator film on said second conductor film over said entire substrate;
(h) forming a second patterned mask on said second insulator film;
(i) patterning said second insulator film and said second conductor film using said second mask to produce second capacitor electrodes and second dielectrics in said capacitor areas, and gate electrodes ad protection insulators in said IGFET areas;
said second insulator film, said second conductor film, and said patterned first insulator film being removed in said bipolar transistor areas;
(j) forming pairs of source/drain regions in said respective second active regions in self-alignment to said gate electrodes;
(k) forming a first interlayer insulator film over said entire substrate, said first interlayer insulator film covering said second dielectrics in said capacitor areas, said patterned first conductor film in said bipolar transistor areas, and said protection insulators in sad IGPET areas;
(l) making first windows, second windows and third windows in said first interlayer insulator film, said first windows exposing said respective second dielectrics, said second windows exposing, said first patterned conductor film and being located over said respective base regions, and said third windows exposing said respective pairs of source/drain regions;
(m) making fourth windows in said first patterned conductor film in said bipolar transistor areas, said fourth windows exposing said base regions and being communicated with said respective second windows;
said remaining first conductor film constituting said base electrodes;
(n) forming a third conductor film over said substrate, said third conductor film being contacted with said second dielectrics through said first windows in said capacitor areas, with said base regions through said second windows and said corresponding fourth windows in said respective bipolar transistor areas, and with said pairs of source/drain regions in said IGFET areas;
(o) patterning said third conductor film to produce third capacitor electrodes in said capacitor areas, emitter electrodes in said bipolar transistor areas, and pairs of source/drain electrodes in said IGFET areas;
(p) forming emitter regions in said respective first active regions in said bipolar transistor areas by heat treatment, said emitter regions being produced by diffusion of an impurity doped in said emitter electrodes;
(q) forming a second interlayer insulator film over said entire substrate, said second interlayer insulator film covering said third conductors in said capacitor areas, said emitter electrodes and said exposing first interlayer insulator film in said bipolar transistor areas, and said pairs of source/drain electrodes and said exposing said first interlayer insulator film in said IGFET areas;
(r) making first holes exposing said respective first conductors, second holes exposing said respective second conductors, third holes exposing said respective third conductors, fourth holes exposing said respective base electrodes, fifth holes exposing said respective emitter electrodes, and sixth holes exposing said respective pairs of said source/drain electrodes in said second interlayer insulator film;
and
(s) forming a patterned interconnection film on said second interlayer insulator film over said entire substrate;
said interconnection film having first parts contacted with said first conductors through said respective first holes and with said third conductors through said respective third conductors in said capacitor areas:
said interconnection film having second parts contacted with said second conductors through said respective second holes in said capacitor areas;
said interconnection film having third parts contacted with said base electrodes through said respective fourth holes in said bipolar transistor areas;
said interconnection film having fourth parts contacted with said emitter electrodes through said respective fifth holes in said bipolar transistor areas;
said interconnection film having fifth parts contacted with said respective pairs of said source/drain electrodes through said respective sixth holes.

28 more elements

Dependencies are inferred from the claim text.