Capacitor-couple electrostatic discharge protection circuit

A capacitor-couple electrostatic discharge (ESD) protection circuit adapted to be used in an integrated circuit (IC) and connected between an internal circuit and an output pad of said IC for protecting an output buffer, said capacitor-couple ESD protection circuit comprising:

• an ESD bypass device electrically connected to said output pad for bypassing said ESD current inputted from said output pad, said device comprising an NMOS transistor having a gate for bypassing said ESD current when said ESD voltage occurring at said input pad is in a first polarity state and a PMOS transistor or having a gate for bypassing said ESD current when said ESD voltage occurring at said input pad is in a second polarity state;
• an ESD bypass device electrically connected to said internal circuit for protecting said internal circuit by bypassing said ESD current;
• a capacitor-couple circuit electrically connected to said ESD bypass device and coupling a portion of ESD voltage to said gate of said NMOS transistor when said ESD voltage occurring at said output pad is in a first polarity state, and said gate of said PMOS transistor when said ESD voltage occurring at said input pad is in said second polarity state;
• and
• a potential leveling device comprising a first diode and a second diode parasitizing to said ESD bypass device for keeping said ESD voltage transmitted for said internal circuit at a low potential level and bypassing said ESD voltage via said first diode when said ESD voltage occurring at said output pad is in a third polarity state and via second diode when said ESD voltage occurring at said input pad is in a fourth polarity state.