US 5,631,579 A · Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages

Abstract

An output buffer circuit operating normally when its supply potential is exceeded by the potential of the bus to which the buffer circuit output is connected. The circuit comprises a p-channel MOS transistor and a first and a second n-channel MOS transistor. The output node of the output buffer circuit is connected not to the p-channel MOS transistor but to the connection point between the source of the first n-channel MOS transistor and the drain of the second n-channel MOS transistor. The threshold potential of the first n-channel MOS transistor is set so that, with the output node in the high-impedance state, the first n-channel MOS transistor is turned off when the output node potential exceeds the supply potential of the output buffer circuit. This prevents the p-channel MOS transistor from getting activated or from being forward-biased between the back gate and the drain or source. Thus no leak current flows when the bus potential becomes higher than the supply potential of the output buffer circuit.

Claims9

Dependent claims

An output buffer circuit for switching the level of an output signal to one of a first logical level, a second logical level and a high-impedance state in response to an externally supplied data signal and control signal, said output buffer circuit comprising:

a p-channel MOS transistor and a first n-channel MOS transistor connected in series between a first supply potential and a second supply potential and turned on and off in accordance with said externally supplied data and control signal;
a second n-channel MOS transistor inserted in series between said p-channel MOS transistor and said first n-channel MOS transistor and turned on and off in accordance with said externally supplied control signal;
an output node connected to the connection point between said first and said second n-channel MOS transistor;
and
voltage converting means for generating a signal having a potential higher than the first supply potential in accordance with said externally supplied control signal, wherein
said second n-channel MOS transistor is an enhancement type transistor, and
the gate of said second n-channel MOS transistor is driven by the signal generated by said voltage converting means.

4 more elements

An output buffer circuit for switching the level of an output signal to one of a first logical level, a second logical level and a high-impedance state in response to a data signal and an output impedance control signal which are externally supplied, said output buffer circuit comprising:

a control circuit receiving said data signal and said output impedance control signal, and outputting first, second and third control signals for controlling the state of said output signal;
a p-channel MOS transistor having the gate coupled to receive said first control signal, and the source coupled to receive a first supply potential;
a first n-channel MOS transistor having the gate coupled to receive said second control signal, and the source coupled to receive a second supply potential;
a second n-channel MOS transistor having the gate coupled to receive said third control signal derived from said output impedance control signal, the drain coupled to the drain of said p-channel MOS transistor, and the source coupled to the drain of said first n-channel MOS transistor;
and
an output node connected to the drain of said first n-channel MOS transistor and to the source of said second n-channel MOS transistor, wherein
said second n-channel MOS transistor is an enhancement type transistor;
said first and said second n-channel MOS transistor turning off in response to said second and third control signals, respectively, during activation of said output impedance control signal,
said second n-channel MOS transistor turning on, said p-channel MOS transistor and said first n-channel MOS transistor turning on/off complementarily in response to said third, first and second control signals, respectively, during inactivation of said output impedance control signal, and
said control circuit includes:
a first inverter having an input coupled to receive said data signal, and an output coupled to the gate of said p-channel MOS transistor;
a two-input NOR circuit having a first input coupled to receive said data signal, a second input coupled to receive said output impedance control signal, and an output coupled to the gate of said first n-channel MOS transistor;
and
a second inverter having an input coupled to receive said output impedance control signal, and an output coupled to the gate of said second n-channel MOS transistor.

11 more elements

a control circuit receiving said data signal and said output impedance control signal, and outputting first, second and third control signals for controlling the state of said output signal;
a p-channel MOS transistor having the gate coupled to receive said first control signal, and the source coupled to receive a first supply potential;
a first n-channel MOS transistor having the gate coupled to receive said second control signal, and the source coupled to receive a second supply potential;
a second n-channel MOS transistor having the gate coupled to receive said third control signal derived from said output impedance control signal, the drain coupled to the drain of said p-channel MOS transistor, and the source coupled to the drain of said first n-channel MOS transistor;
an output node connected to the drain of said first n-channel MOS transistor and to the source of said second n-channel MOS transistor;
and
voltage converting means for generating a signal having potential higher than said first supply potential, wherein
the gate of said second n-channel MOS transistor is driven by the signal generated by said voltage converting means, and
said second n-channel MOS transistor is an enhancement type transistor,
said first and said second n-channel MOS transistor turning off in response to said second and third control signals, respectively, during activation of said output impedance control signal, and
said second n-channel MOS transistor turning on, said p-channel MOS transistor and said first n-channel MOS transistor turning on/off complementarily in response to said third, first and second control signals, respectively, during inactivation of said output impedance control signal.

8 more elements

a control circuit receiving said data signal and said output impedance control signal, and outputting first, second and third control signals for controlling the state of said output signal;
a p-channel MOS transistor having the gate coupled to receive said first control signal, and the source coupled to receive a first supply potential;
a first n-channel MOS transistor having the gate coupled to receive said second control signal, the drain connected to the drain of said p-channel MOS transistor, and the source coupled to receive a second supply potential;
a second n-channel MOS transistor having the gate coupled to receive said third control signal, and the drain connected to the drain of said p-channel MOS transistor and to the drain of said first n-channel MOS transistor;
and
an output node connected to the source of said second n-channel MOS transistor;
and
voltage converting means for generating a signal having potential higher than said first supply potential, wherein
the gate of said second n-channel MOS transistor is driven by the signal generated by said voltage converting means,
said second n-channel MOS transistor is an enhancement type transistor,
said second n-channel MOS transistor turning off in response to said third control signal during activation of said output impedance control signal, and
said second n-channel MOS transistor turning on, said p-channel MOS transistor and said first n-channel MOS transistor turning on/off complementarily in response to said third, first and second control signals respectively, during inactivation of said output impedance control signal.

9 more elements

Dependencies are inferred from the claim text.

Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages

Life of this patent

Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages

Life of this patent

Abstract

Claims9