Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation

A semiconductor device comprising:

• a substrate having a surface;
• a first doped region formed within the substrate, the first doped region being a P doped region which is used to support formation of N type source and drain regions within the P doped region, the P doped region forming an N-channel region
• a second doped region formed within the substrate, the second doped region being an N doped region which is used to support formation of P type source and drain regions within the N doped region, the N doped region forming a P-channel region;
• a dielectric layer formed overlying the surface of the substrate;
• a first conductive region formed overlying the dielectric layer and overlying the N-channel region;
• a second conductive region formed overlying the dielectric layer, laterally separated from the first conductive region, and overlying the P-channel region;
• a first metal conductor for providing a power supply potential, the first metal conductor being coupled to the first conductive region to form a capacitor between the first conductive region and the first doped region;
• and
• a second metal conductor for supplying a ground potential, the second metal conductor being coupled to the second conductive region to form a capacitor between the second conductive region and the second doped region.

A standard cell layout comprising:

• a substrate;
• a dielectric layer formed overlying the substrate;
• a power supply conductor overlying the dielectric layer;
• a ground conductor overlying the dielectric layer;
• a first active region defined within the substrate and being coupled to the power supply conductor through a first plurality of contact openings formed through the dielectric layer, the first active region being of a first conductivity type;
• a second active region defined within the substrate and being laterally adjacent the first active region, the second active region being coupled to the ground conductor through a second plurality of contact openings formed through the dielectric layer, the second active being of a second conductivity type which is different from the first conductivity type;
• a first conductive layer overlying the first active region, being separated form the first active region by a first gate dielectric region, and being coupled to the ground supply conductor through a third plurality of contact openings formed through the dielectric layer;
• and
• a second conductive layer overlying the second active region, being separated form the second active region by a second gate dielectric region, and being coupled to the power supply conductor through a fourth plurality of contact openings formed through the dielectric layer.

A semiconductor device comprising:

• a substrate having a surface;
• a first doped region formed within the substrate which is an N type transistor region;
• a second doped region formed within the substrate which is a P type transistor region;
• a dielectric layer formed overlying the surface of the substrate;
• a first conductive region formed overlying the dielectric layer and in close proximity to the first doped region;
• a second conductive region formed overlying the dielectric layer, laterally separated from the first conductive region, and in close proximity to the second doped region;
• a first metal conductor for providing a power supply potential, the first metal conductor being coupled to the first conductive region to form a capacitor between the first conductive region and the first doped region;
• a second metal conductor for supplying a ground potential, the second metal conductor being coupled to the second conductive region to form a capacitor between the second conductive region and the second doped region;
• and
• wherein replicas of the semiconductor device are automatically placed by a place and route tool into a plurality of unused substrate areas on the surface of an integrated circuit die, wherein the plurality of unused substrate areas are areas not occupied by other standard logic cells, whereby the plurality of unused areas are coupled for a purpose of reducing power supply and ground supply noise via on-chip capacitors.