Read-only-memory having both bipolar and channel transistors
AssigneeUnited Microelectronics Corp.
InventorChen-Chung Hsu
Life of this patent
Estimating the term…
Abstract
A structure for a read-only-memory (ROM) having both bipolar and channel transistors as memory cells to achieve efficient space utilization and higher density of ROM elements. The channel transistors include bit lines and word lines, with a threshold voltage at about 0.7 V. By implanting impurities into predetermined channel regions, memory cells become conductive or non-conductive. Bipolar transistors are formed in predetermined intersections of bit lines and word lines with a threshold voltage of about 3 V to 5 V, which can be treated as conductive memory cells that conduct current under 5 V operating voltage. Intersections of bit lines and word lines without bipolar transistors formed therein can be treated as non-conductive memory cells.
Claims11
A structure for a read-only-memory on a semiconductor substrate comprising:
- a plurality of buried bit lines of a first conductivity type, equally spaced on the substrate, forming channel regions therebetween, predetermined ones of which to be later coded being implanted with impurities of a second conductivity type to become non-conductive;
- a gate oxide layer formed on said channel regions;
- a plurality of thick oxide layers formed on said buried bit lines, predetermined ones of said thick oxide layers having openings therein;
- base regions of the second conductivity type and emitter regions of the first conductivity type, formed in said buried bit lines beneath said openings, constructing bipolar transistors with said buried bit lines as collector regions of the first conductivity type;
- and
- a plurality of word lines, formed above said gate oxide layer and said thick oxide layers and across said buried bit lines to construct channel transistors with said buried bit lines and said channel regions, said word lines being connected with said emitter regions through said openings.
A memory array comprising:
- a semiconductor substrate having a plurality of buried bit lines formed therein and a plurality of word lines formed thereon, said word lines and buried bit lines intersecting with each other to construct channel-transistor memory cells;
- and
- a plurality of bipolar-transistor memory cells formed in said buried bit lines at the intersections of said word lines and buried bit lines.
A read-only memory structure comprising:
- a substrate;
- a plurality of buried bit lines formed in said substrate;
- an oxide layer formed over said buried bit lines;
- at least one word line formed on said oxide layer and crossing said buried bit lines;
- a plurality of channel regions respectively formed in said substrate between said buried bit lines and below said word line so as to define a plurality of channel transistor memory cells;
- and
- at least one bipolar transistor memory cell formed in said substrate at an intersection of one of said buried bit lines and said word line, said one buried bit line connected to a collector region thereof, said word line connected to an emitter region thereof through an opening in said oxide layer.
Dependencies are inferred from the claim text.