US 5,631,483 A · Power device integrated structure with low saturation voltage

Abstract

A power device integrated structure includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type superimposed over the substrate, a plurality of first doped regions of the first conductivity type formed in the semiconductor layer, and a respective plurality of second doped regions of the second conductivity type formed inside the first doped regions. The power device includes: a power MOSFET having a fisrt electrode region formed by the second doped regions and a second electrode region formed by the semiconductor layer; a first bipolar junction transistor having an emitter, a base and a collector respectively formed by the substrate, the semiconductor layer and the first doped regions; and a second bipolar junction transistor having an emitter, a base and a collector respectively formed by the second doped regions, the first doped regions and the semiconductor layer. The doping profiles of the semiconductor substrate, the semiconductor layer, the first doped regions and the second doped regions are such that the first and second bipolar junction transistors have respective first and second common base current gains sufficiently high to cause the bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate into the semiconductor layer and from the second doped regions, through the first doped regions, into the semiconductor layer to modulate the conductivity of the second electrode of the power MOSFET; the fast and second common base current gains summed are less than unity to prevent a parasitic thyristor from triggering on.

Claims15

Dependent claims

A power device integrated structure comprising a semiconductor substrate of a first conductivity type, a semiconductor layer of a second, opposite conductivity type superimposed over said substrate, a plurality of first doped regions of the first conductivity type formed in said semiconductor layer, and a respective plurality of second doped regions of the second conductivity type formed inside said first doped regions, the power device comprising:

a power MOSFET having a first electrode region formed by the second doped regions and a second electrode region formed by the semiconductor layer;
a first bipolar junction transistor having an emitter, a base and a collector respectively formed by the substrate, the semiconductor layer and the first doped regions;
and
a second bipolar junction transistor having an emitter, a base and a collector respectively formed by the second doped regions, the first doped regions and the semiconductor layer,
wherein the doping profiles of the semiconductor substrate, the semiconductor layer, the first doped regions and the second doped regions are such that the first and second bipolar junction transistors have respective first and second common base current gains sufficiently high to cause said bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate into the semiconductor layer and from the second doped regions, through the first doped regions, into the semiconductor layer, respectively, to modulate the conductivity of the second electrode of the power MOSFET, the sum of the common base current gains of the first and second bipolar junction transistors being less than unity to prevent a parasitic thyristor, formed by said first and second bipolar junction transistors, from triggering on.

2 more elements

An integrated power device comprising:

a semiconductor substrate of a first conductivity type;
a semiconductor layer of a second conductivity type superimposed over said substrate;
a plurality of first doped regions of the first conductivity type formed in said semiconductor layer;
a plurality of second doped regions of the second conductivity type, each one of the plurality of second doped regions of the second conductivity type being formed inside a corresponding one of the plurality of first doped regions;
wherein a power MOSFET is formed in the integrated power device having a first electrode region formed by the plurality of second doped regions, and a second electrode region formed by the semiconductor layer, the MOSFET having an on state in which a conductive path is formed between its first and second electrode regions;
wherein a first bipolar junction transistor is formed in the integrated power device having an emitter, a base and a collector respectively formed by the plurality of second doped regions, the plurality of first doped regions and the semiconductor layer;
wherein a second bipolar junction transistor is formed in the integrated power device having an emitter, a base and a collector respectively formed by the plurality of second doped regions, the plurality of first doped regions and the semiconductor layer, the first and second bipolar junction transistors forming a parasitic thyristor in the integrated power device;
and
means for biasing the first and second bipolar junction transistors in a high injection region during the on state of the MOSFET device, so that carriers are injected from the substrate and from the second doped regions into the semiconductor layer to modulate the conductivity of the second electrode of the power MOSFET, the means for biasing including means for preventing the parasitic thyristor from triggering on.

6 more elements

Dependencies are inferred from the claim text.

Power device integrated structure with low saturation voltage

Life of this patent

Power device integrated structure with low saturation voltage

Life of this patent

Abstract

Claims15