US 5,631,482 A · Flash EEPROM memory cell with polysilicon source/drain

Abstract

A method for fabricating an MOSFET device on a lightly doped semiconductor substrate with a first dielectric layer thereon comprises forming a floating gate layer over the first dielectric layer. The floating gate layer is formed into a floating gate line. A doped source region and a doped drain region in the substrate are formed by ion implantation adjacent to the periphery of the floating gate line. The first dielectric layer is etched, exposing the surface of the substrate and the surface of the source region and the drain region aside from the floating gate line. Textured dielectric spacers are formed about the periphery of the floating gate line. Polycrystalline spacers are formed about the periphery of the polysilicon oxide dielectric spacers in electrical contact with the doped regions. The floating gate layer and the dielectric layer and the polysilicon layer are etched to separate the floating gate line into separate floating gates with the spacers separated, forming a blanket interconductor dielectric layer over the device. A blanket deposit of a conductor layer is formed over the interconductor dielectric layer and a control gate mask on the device is used to pattern the conductor layer by etching away portions of the conductor layer unprotected by the control gate mask.

Claims8

Dependent claims

A MOSFET device formed on a semiconductor substrate comprising;

a stack of a first dielectric layer on said substrate, and a floating gate layer over said first dielectric layer;
doped source and drain regions formed in said substrate adjacent to said floating gate;
dielectric spacers extending vertically alongside of said floating gate and laterally over said doped source and drain regions, said dielectric spacers having asperities with a height of at least 20 .ANG.;
polysilicon spacers formed alongside said dielectric spacers, said polysilicon spacers in electrical contact with said doped source and drain regions;
a blanket dielectric layer over said floating gate and said polysilicon spacers;
and
a control gate formed over said blanket dielectric layer above said floating gate.

4 more elements

Dependencies are inferred from the claim text.

Flash EEPROM memory cell with polysilicon source/drain

Life of this patent

Flash EEPROM memory cell with polysilicon source/drain

Life of this patent

Abstract

Claims8