Flat-cell mask ROM integrated circuit

A semiconductor device formed on a semiconductor substrate,

• individual buried bit lines formed below the surface of said semiconductor substrate comprising an individual source region and an individual drain region below the surface of said semiconductor substrate with an oxide structure formed over said buried bit lines,
• a gate oxide layer covering said substrate,
• a first conductive structure on said gate oxide layer formed of polysilicon patterned into segments,
• an insulating structure in contact with said first conductive structure formed between said segments,
• material removed from the surface of said first conductive structure to expose at least a portion of the surface beneath said first conductive structure,
• a metallic structure formed on the remaining structure on said semiconductor substrate, said metallic structure having an edge juxtaposed with said individual source and said individual drain regions in said buried bit lines, and
• said metallic structure formed over the top of said first conductive structure and said insulating structure,
• whereby a compound conductive structure is provided on said semiconductor substrate.

A semiconductor device formed on a semiconductor substrate,

• individual buried bit lines formed below the surface of said semiconductor substrate comprising individual source and drain regions below the surface of said semiconductor substrate with an oxide structure formed over said buried bit lines,
• a gate oxide layer covering said substrate,
• a first conductive structure on said gate oxide layer formed of polysilicon patterned into segments,
• an insulating structure composed of BPSG in contact with said first conductive structure formed between said segments,
• material removed from the surface of said first conductive structure to expose at least a portion of the surface beneath said first conductive structure,
• a metallic structure formed over the top of said first conductive structure and said insulating structure on the remaining structure on said semiconductor substrate,
• said metallic structure having an edge juxtaposed with said individual source region and said individual drain region in said buried bit lines,
• a sidewall structure comprising a nitride spacer formed adjacent to said metallic structure, and
• whereby a compound conductive structure is provided on said semiconductor substrate.