Semiconductor integrated circuits with specific pitch multilevel interconnections
AssigneeNEC Corporation
InventorKoichiro Okumura
Life of this patent
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Abstract
A multilevel interconnection structure for semiconductor integrated circuits has five or more multiple interconnection layers, each of which includes a plurality of interconnections, wherein the lower level interconnections included in first to third interconnection layers form the lowest level interconnection layer have pitches less than 2 micrometers and the high level interconnections included in the remaining interconnection layers have pitches in the range from 2 to 3 micrometers.
Claims8
A multilevel interconnection structure for semiconductor integrated circuits, said structure comprising at least five interconnection layer levels, each of said layers including interconnections at each level, wherein first, second and third lowest level interconnections have a first uniform pitch and are so provided in first, second and third lowest level interconnection layers as to have pitches less than approximately 2 micrometers and ranging from 4.5 to 5.5 times a minimum gate length of MOS field effect transistors of said semiconductor integrated circuits, and remaining higher level interconnections in remaining higher level interconnection layers have a second uniform pitch ranging from approximately 2 micrometers to approximately 3 micrometers.
A multilevel interconnection structure for semiconductor integrated circuits, said structure comprising a plurality of interconnection groups having various levels, wherein a higher level interconnection group has a larger pitch and a larger width than an adjacent lower level interconnection group, said structure comprising at least five level interconnection groups, each of said groups including interconnections at each level, a first, second and third lowest level interconnections provided in first, second and third lowest level interconnection groups have a first uniform pitch of less than approximately 2 micrometers and in a range from 4.5 to 5.5 times of a minimum gate length of MOS field effect transistors of said semiconductor integrated circuits and remaining higher level interconnections in remaining higher level interconnection groups have a second uniform pitch in the range from approximately 2 micrometers to approximately 3 micrometers.
Dependencies are inferred from the claim text.