Low voltage coefficient polysilicon capacitor

A method for forming a double layer polysilicon capacitor comprising:

• forming upon a semiconductor substrate a first polysilicon layer;
• forming directly upon the first polysilicon layer an Inter Polysilicon Dielectric (IPD) layer;
• forming directly upon the Inter Polysilicon Dielectric (IPD) layer a second polysilicon layer;
• forming directly upon the second polysilicon layer an amorphous silicon layer;
• forming directly upon the amorphous silicon layer a metal layer, the metal layer being formed from a metal which forms a metal silicide layer through reaction with the amorphous silicon layer;
• and,
• annealing the semiconductor substrate to form the metal silicide from the amorphous silicon layer and the metal layer, where the thickness of the metal layer and the thickness of the amorphous silicon layer are chosen to form a stoichiometric metal silicide with minimal consumption of the polysilicon layer.

A method for forming a double layer polysilicon capacitor within an integrated circuit comprising:

• forming upon a semiconductor substrate an integrated circuit, the integrated circuit having a minimum of one transistor formed therein;
• forming upon the semiconductor substrate a first polysilicon layer;
• forming directly upon the first polysilicon layer an Inter Polysilicon Dielectric (IPD) layer;
• forming directly upon the Inter Polysilicon Dielectric (IPD) layer a second polysilicon layer;
• forming directly upon the second polysilicon layer an amorphous silicon layer;
• forming directly upon the amorphous silicon layer a metal layer, the metal layer being formed from a metal which forms a metal silicide layer through reaction with the amorphous silicon layer;
• and,
• annealing the semiconductor substrate to form the metal silicide from the amorphous silicon layer and the metal layer, where the thickness of the metal layer and the thickness of the amorphous silicon layer are chosen to form a stoichiometric metal silicide with minimal consumption of the polysilicon layer.