US 5,631,182 AGranted

Method of making a semiconductor memory circuit device

AssigneeHitachi, Ltd.

InventorsNaokatsu Suwanai, Hiroyuki Miyazawa, Atushi Ogishima, Masaki Nagao, Kyoichiro Asayama, Hiroyuki Uchiyama, Yoshiyuki Kaneko, Takashi Yoneoka, Kozo Watanabe, Kazuya Endo, Hiroki Soeda

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Abstract

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

Claims6

Dependent claims

A method for fabricating a semiconductor memory circuit device having an array of memory cells arranged in a matrix form and each consisting of a first MISFET and an information storing capacitor both connected in series with each other, and also having a peripheral circuitry constituted by a plurality of second MISFETs, said method comprising:

(a) a step of forming a first gate electrode of each said first MISFET and a second gate electrode of each said second MISFET over first and second regions, respectively, of a first electroconductivity type semiconductor substrate;
(b) a step of introducing first impurities of a second electroconductivity type, opposite to the first electroconductivity type, into said semiconductor substrate in self-alignment with said first and second gate electrodes, so as to form first semiconductor regions for the first and second MISFETs;
(c) a step of forming a side wall insulating film along end portions of said first and second gate electrodes;
(d) a step of forming a first electrode of said information storing capacitor so as to be in contact with one of the source and drain regions of said first MISFET;
(e) a step of forming a dielectric film and a second electrode of said information storing capacitor on said first electrode;
(f) a step of forming a second insulating film over said first and second regions of said semiconductor substrate, overlying the second gate electrode over the second region and overlying the second electrode over the first region;
(g) a step of forming a wiring layer over said second insulating film in said first and second regions;
(h) a step of introducing second impurities of said second electroconductivity type into said semiconductor substrate over said second region in self-alignment with said second gate electrode and said side wall insulating film, so as to form second semiconductor regions for said second MISFETs, after having carried out processes (a) and (c);
and
(i) a step of forming a third insulating film overlying only said second region,
wherein said process (h) is carried out prior to said processes (i) and (f), and said process (i) is carried out between said processes (c) and (g).

8 more elements

A method for fabricating a semiconductor memory circuit device having an array of memory cells arranged in a matrix form, each of said memory cells including a first MISFET and an information storing capacitor connected in series with each other, the device also having peripheral circuitry constituted by a plurality of second MISFETs, comprising the steps of:

(a) forming a first gate electrode of each first MISFET and a second gate electrode of each second MISFET over a first region and a second region, respectively, of a semiconductor substrate;
(b) introducing first impurities of N-conductivity type into said semiconductor substrate in self-alignment with said first and second gate electrodes in said first and second regions, so as to form a source region and a drain region for said first and second MISFETs;
(c) forming a first electrode of said information storing capacitor so as to be in contact with one of the source region and the drain region of said first MISFET, said first electrode extending over said first gate electrode;
(d) forming a dielectric film and a second electrode of said information storing capacitor respectively on said first electrode and on said dielectric film;
(e) forming a first insulating film over the first and second regions of said semiconductor substrate, overlying the second gate electrode over the second region and overlying the second electrode over the first region;
(f) forming a second insulating film over said second region, selectively, so as to diminish a difference in height between said first and second regions, as compared to a difference in height if said second insulating film were not formed;
and
(g) forming a wiring layer overlying said first insulating film over the first and second regions;
wherein said step (f) is performed between the steps (d) and (g).

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/327,861Filed 18 Oct 1994 · division
Priority: JP 2-32912230 Nov 1990
Granted: 20 May 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10B 12/01
Dynamic random access memory [DRAM] devices: manufacture or treatment
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10B 12/31
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: having a storage electrode stacked over the transistor
H10B
Electronic memory devices

Family

Serial799,541Parent of this division · filed 27 Nov 1991
Serial104,014Parent of this division · filed 10 Aug 1993
US 5,389,558 AParent of this division
US 5,237,187 AParent of this division
US 5,631,182 AThis patent

From the US filing history. Foreign family members aren’t listed.