Method of fabricating high threshold metal oxide silicon read-only-memory transistors
AssigneeZilog, Inc.
InventorsAlex Gyure, John Berg, Damian Carver, Pete Manos
Life of this patent
Estimating the term…
Abstract
A method of forming ROM transistor memory cell including not forming lightly doped regions in the semiconductor substrate for some of the memory cells so as to form one type of memory cell and forming the lightly doped regions in another type of memory cell.
Claims22
A method of forming a read-only-memory circuit including memory locations on a silicon substrate comprising:
- forming polysilicon lines at the memory locations;
- implanting lightly doped regions in the silicon substrate at some but not all of the memory locations, this lightly doped regions implanting step being self-aligned around the polysilicon lines at the some but not all the memory locations;
- thereafter, forming barrier layers on the polysilicon lines;
- and
- implanting heavily doped regions in the silicon substrate at the memory locations, this heavily doped regions implanting step being self-aligned around the barrier layers on the polysilicon lines;
- wherein a memory cell of one type is formed at the some but not all memory locations where the lightly doped regions are formed and a memory cell of another type is formed at other memory locations where lightly doped regions are not formed.
The method of claim 8, wherein the phosphorous ions implanting step comprises doping in the range of around 2-9 * 10.sup.13 phosphorous ions per square centimeter to form the lightly doped regions.
A method of forming a read-only-memory circuit including memory locations on a silicon substrate comprising:
- forming polysilicon lines at the memory locations;
- forming lightly doped regions by implanting donor ions in the silicon substrate at the memory locations, this donor ions implanting step being self-aligned around the polysilicon lines;
- implanting acceptor ions into the lightly doped regions at some but not all of the memory locations, this acceptor ions implanting step being self-aligned around the polysilicon lines at the some but not all the memory locations;
- thereafter, forming barrier layers on the polysilicon lines;
- and
- implanting heavily doped regions in the silicon substrate at the memory locations, this heavily doped regions implanting step being self-aligned around the barrier layers on the polysilicon lines;
- wherein a memory cell of one type is formed at other memory locations where acceptor atoms are not implanted and a memory cell of another type is formed at the some but not all memory locations where the acceptor ions are implanted.
A method of forming a read-only-memory circuit including memory locations on a silicon substrate comprising:
- forming polysilicon lines at the memory locations;
- forming lightly doped regions by implanting a first dopant type of ions in the silicon substrate at the memory locations, this first dopant type of ions implanting step being self-aligned around the polysilicon lines;
- implanting a second dopant type of ions into the lightly doped regions at some but not all of the memory locations, this second dopant type of ions implanting step being self-aligned around the polysilicon lines at the some but not all the memory locations;
- thereafter, forming barrier layers on the polysilicon lines;
- and
- implanting heavily doped regions in the silicon substrate at the memory locations, this heavily doped regions implanting step being self-aligned around the barrier layers on the polysilicon lines;
- wherein a memory cell of one type is formed at other memory locations where the second dopant type of ions are not implanted and a memory cell of another type is formed at the some but not all memory locations where the second dopant type of ions are implanted.
Dependencies are inferred from the claim text.