US 5,627,097 A · Method for making CMOS device having reduced parasitic capacitance

Abstract

A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).

Claims13

Dependent claims

A process for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate having an undoped silicon layer overlying a buried layer;
forming a trench isolation structure in the undoped silicon layer to define an active region therein;
forming a masking layer on the undoped silicon layer, the masking layer having an opening therein exposing a channel portion of the active region;
doping the channel portion with a first dopant, using the masking layer as a doping mask, wherein the first dopant extends from an upper surface of the undoped silicon layer to the buried layer;
depositing a layer of polycrystalline silicon to overlie the masking layer and the channel portion;
planarizing the polycrystalline silicon to form a gate electrode overlying the channel portion;
removing the masking layer;
and
forming source and drain regions in the undoped silicon layer on either side of the gate electrode, wherein the source and drain regions are vertically separated from the buried layer by a portion of the undoped silicon layer.

6 more elements

A process for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate having a surface;
forming a first buried layer of a first conductivity type at the surface;
forming a second buried layer of a second conductivity type at the surface adjacent to the first buried layer;
forming an undoped epitaxial layer overlying the first and second buried layers;
forming an isolation region in the undoped epitaxial layer to define a first active region overlying the first buried layer and a second active region overlying the second buried layer;
forming a masking pattern overlying the undoped epitaxial layer and the isolation region, the masking pattern having a first opening therein exposing a channel portion of the first active region and a second opening therein exposing a channel portion of the second active region;
doping the channel portion of the first active region with a dopant of the first conductivity type;
doping the channel portion of the second active region with a dopant of the second conductivity type;
forming a first gate electrode in the first opening and a second gate electrode in the second opening;
forming source and drain regions of the second conductivity type on either side of the first gate electrode;
and
forming source and drain regions of the first conductivity type on either side of the second gate electrode,
wherein the source and drain regions of the second conductivity type are spaced apart from the first buried layer by a first portion of the undoped epitaxial layer, and
wherein the source and drain regions of the first conductivity type are spaced apart frozen the second buried layer by a second portion of the undoped epitaxial layer.

11 more elements

Dependencies are inferred from the claim text.

Method for making CMOS device having reduced parasitic capacitance

Life of this patent

Method for making CMOS device having reduced parasitic capacitance

Life of this patent

Abstract

Claims13