Deep trench dram process on SOI for low leakage DRAM cell

A method for forming a dynamic random access memory cell (DRAM), comprising the steps of:

• doping a silicon on isolator (SOI) substrate with dopants of a first conductivity type;
• forming an SOI oxide layer on said substrate;
• forming a silicon device layer over said SOI oxide layer;
• doping said silicon device layer with dopants of a second conductivity type opposite that of said first conductivity type;
• forming a pad nitride layer over said silicon device layer;
• forming a TEOS etch mask layer over said pad nitride layer;
• etching a trench into said substrate at a first region thereof;
• forming a dielectric layer on interior walls of said trench;
• filling said trench to the top level of said TEOS etch mask layer with a polysilicon material doped to said first conductivity type;
• removing said TEOS etch mask layer;
• recess etching said polysilicon material down to about the mid-level of said SOI oxide layer;
• isotropic etching away said dielectric layer from end portions of said silicon device layers;
• refilling said trench with intrinsic polysilicon material above the remaining first conductivity type doped polysilicon material;
• recess etching said intrinsic polysilicon material down to about the middle of said silicon device layer, thereby leaving a polysilicon stud protruding from said trench;
• etching away said pad nitride layer and said silicon device layer on one side of said trench, using the associated portion of said SOI oxide layer as an etch stop;
• thermally oxidizing said polysilicon stud, while permitting outdiffusion of dopant material from the underlying doped polysilicon material, into and through a remaining portion of initially intrinsic polysilicon material, into an adjacent portion of said silicon device layer on an opposite side of said trench for providing a buried strap;
• chemical vapor depositing (CVD) an oxide layer over said polysilicon stud and said SOI layer adjacent said one side of said trench to above the top level of said silicon device layer adjacent the opposite side of said trench;
• planarizing said CVD oxide to the level of the remaining portion of said silicon device layer;
• oxidizing said silicon device layer with gate sacrificial oxide;
• and
• implanting an MOS transistor switch including adjacent drain, channel, and source regions in said silicon device layer, with a gate stack consisting of a first gate layer of said first conductivity overlying said channel region, and portions of said drain and source regions, and an intrinsic second gate layer overlying said first gate layer.