Mask ROM process for making a ROM with a trench shaped channel
AssigneeUnited Microelectronics Corp.
InventorGary Hong
Life of this patent
Estimating the term…
Abstract
A memory cell, and process for making it, having a long channel and narrow buried bit line is disclosed. The memory cell is formed in a substrate having a first dopant type. A trench is defined in the substrate. Source/drain regions of a second dopant type are formed on the surface of the substrate to each side of the trench. A gate oxide layer is formed over the substrate and a polysilicon wordline deposited over the gate oxide layer. A channel is defined along the walls of the trench. Ions are implanted in the bottom of the trench defining the channel for a cell that is selected to be in the off state. The long channel and narrow bit line of these memory cells overcome the problem of high bit line resistance and low junction breakdown voltage found in conventional memory cells.
Claims9
A process for making a memory array comprising:
- forming a first doped layer having a second conductivity type in a substrate having a first conductivity type,
- forming and patterning a first photo-resist layer over said first doped layer,
- using said patterned first photo-resist layer as a mask to form a trench shaped channel having two vertical sides, each side having substantially the same height, and a bottom having a width, in said first doped layer and said substrate to form buried bit source and drain lines in said first doped layer, said source and drain lines being separated by said channel so that an effective channel length of said channel between said source line and said drain line is approximately equivalent to twice the height of said vertical side of said channel plus the width of said bottom of said channel,
- growing an oxide layer over said substrate including said first doped layer, and
- depositing a word line over said oxide layer.
Dependencies are inferred from the claim text.