High speed flip-flop for gate array

The method for latching a logic state in response to the generation of transitions in a clock signal, comprising the steps of;

• inputting an input signal having an input logic state to an input node;
• transferring a master logic state that represents the input logic state to at least one master storage node, the step of transferring operating in response to a first transition of the clock signal;
• latching the master logic state to the master storage node;
• transferring a slave logic state representative of the master logic state to a single slave storage node in response to a second transition of the clock signal;
• latching the slave logic state to the single slave storage node;
• transferring an inverse slave logic State representative of the complement of the master logic state to an inverse slave storage node in response to said second transition of the clock signal:
• latching the inverse slave logic state to the inverse slave storage node;
• outputting the slave logic state on the slave storage node to a first output:
• and
• outputting the inverse slave logic state on the slave storage node to a second output.

A memory device comprising:

• an inverter having an input and an output;
• a p-channel transistor having a gate, a source and a drain wherein said gate is coupled to the output of said inverter, wherein said source is coupled to a first voltage supply and said drain is coupled to the input of said inverter;
• a first n-channel transistor having a gate, a source and a drain wherein said drain is coupled to the drain of said p-channel transistor and said gate is coupled to the gate of the p-channel transistor;
• and
• a second n-channel transistor having a gate, a source and a drain wherein said drain is coupled to the source of said first n-channel transistor, said source is coupled to a second voltage supply and said gate is coupled so as to receive an enable signal.

Sequential circuitry for latching a logic state in response to a clock signal, comprising:

• an input node for receiving an input signal having an input logic state;
• a master storage node for storing a master logic state;
• a slave storage node for storing a slave logic state;
• first transfer circuitry coupled between said input node and said master storage node;
• a master latch coupled to said master storage node, said master latch comprising:
• an inverter having an input and an output;
• a p-channel transistor having a gate, a source and a drain wherein said gate is coupled to the output of said inverter, wherein said source is coupled to a first voltage supply and said drain is coupled to the input of said inverter;
• a first n-channel transistor having a gate, a source and a drain wherein said drain is coupled to the drain of said p-channel transistor and said gate is coupled to the gate of said p-Channel transistor;
• and
• a second n-channel transistor having a gate, a source and a drain wherein said drain is coupled to the source of said first n-channel transistor, said source is coupled to a second voltage supply and said gate is coupled so as to receive said clock signal;
• second transfer circuitry coupled between said master storage node and said slave storage node;
• and
• a slave latch coupled to said slave latch node.

Sequential circuitry for latching a logic state in response to an enable signal, comprising:

• an input node for receiving an input signal having an input logic state;
• a master storage node for storing a master logic state;
• a slave storage node for storing a slave logic state;
• first transfer circuitry coupled between said input node and said master storage node;
• a master latch coupled to said master storage node;
• second transfer circuitry coupled between said master storage node and said slave storage node;
• and
• a slave latch coupled to said slave latch node, said slave latch comprising:
• an inverter having an input and an output;
• a p-channel transistor having a gate, a source and a drain wherein said gate is coupled to the output of said inverter, wherein said source is coupled to a first voltage supply and said drain is coupled to the input of said inverter;
• a first n-channel transistor having a gate, a source and a drain wherein said drain is coupled to the drain of said p-channel transistor and said gate is coupled to the gate of the p-channel transistor;
• and
• a second n-channel transistor having a gate, a source and a drain wherein said drain is coupled to the source of said first n-channel transistor said source is coupled to a second voltage supply, and said gate is coupled so as to receive said enable signal.

A master slave flip-flop comprising:

• an input node;
• a master storage node;
• an output node;
• first transfer circuitry coupled between said input node and said master storage node for transferring a logic state present at said input node to said master storage node upon receipt of a first clock signal;
• a master latch for latching a master logic state to said master storage node;
• second transfer circuitry with an input coupled to said master storage node and an output coupled directly to said output node wherein said second transfer circuitry transfers said master logic state to said output node upon receipt of a second clock signal said second transfer circuitry comprising a transmission gate;
• and
• a slave latch for latching said master logic state to said output node upon receipt of said clock signal, said slave latch comprising a static latch.