Electrical test structure and method for measuring the relative locations of conducting features on an insulating substrate

Abstract

A test structure for submicrometer metrology as used in integral circuit manufacture comprises a bridge conductor divided into three segments by pairs of voltage taps. A first segment has no intermediate taps; a second segment has a number of dummy taps intermediate its ends; and a third segment has a single central tap, which may typically be formed in a different step than the remainder of the test structure, intermediate its ends. Preferably, the central tap extends from the same side of the bridge conductor as the taps at the ends of the third segment thereof. In order to evaluate a manufacturing operation, for example, to monitor the accuracy of registration of successive manufacturing steps, test signals are applied successively between the pairs of pads. Comparison of the response of the first and second segments to the test signals allows evaluation of the segment-shortening effect of the taps; comparison of the response of the two portions of the third segment to the test signals allows evaluation of their lengths, and thus of the offset, that is, the accuracy of registration of the step used to form the central tap. A plurality of substantially identical test structures are formed, for example, on an integrated circuit substrate. Offsets measured with respect to each of the substrates are summed using a least-squares technique, to allow separation of tool-wide misalignment errors and errors in the generation of a particular pattern or similar tool used to form a test structure. By summing the offsets measured with respect to a large number of test structures, random errors due to the presence of dust or other contaminants on the tools are effectively eliminated.

Dependencies are inferred from the claim text.