Semiconductor memory device with internal self-refreshing

A semiconductor memory device having internal self refreshing comprising:

• a plurality of memory cell arrays, each array comprising a matrix of rows and columns, a row of memory cells comprising a word line, each memory cell comprising a single transistor;
• a plurality of address terminals for receiving row address, column address, and memory array address signals, respectively;
• a plurality of row address decoders responsive to row address signals for generating a selected address indicative of a word line of a memory array where data is to be written into or read out of;
• a plurality of refresh decoders, one refresh decoder for each memory cell array;
• a plurality of sense amplifiers, one amplifier coupled to each memory cell array, the amplifier amplifying a signal emitted from each memory cell in a word line indicative of data stored in the cell, upon activation of the word line by the refresh decoder, the amplifier reading data stored in the word line, amplifying the data, and writing the amplified data into the word line for refreshing the data, the amplifier enabling data stored in the word line being refreshed to be read out of the device;
• an internal clock generator for generating and adjusting a self-refreshing time period, the clock generator provided with programmable elements comprising fuse means, so that the fuse means may be opened for adjusting the self-refreshing time period;
• an address counter receiving output pulses from the clock generator for incrementing the counter, the counter generating an internal refreshing address and transmitting a refresh signal to a corresponding one of the refresh decoders for activating a memory word line corresponding to the refreshing address, the refresh decoders activating the word line so that the corresponding sense amplifier refreshes the data stored in the word line, the counter being incremented, such that once the data stored in a first word line of a first one of the memory cell arrays is refreshed, the internal refreshing address is incremented to a first word line of a second memory cell array, each word line being refreshed during one self-refreshing time period;
• a programmable timer for counting down a write delay time period;
• control logic coupled to the timer;
• and
• a comparator coupled to the address counter and to row address and memory address terminals, the comparator comparing an external address to be written, indicated by the row address signal, and the internal refreshing address generated by the counter,
• whereby if the comparator detects that the external address to be written matches the internal address being refreshed, the comparator transmits a signal to the control logic which signals the timer to begin counting down the write delay time period, the control logic enables the data to be written to the refreshed address upon the termination of the write delay time period, such that a maximum write delay time period is equal to one self-refreshing time period.

A semiconductor memory device having internal self-refreshing comprising:

• a plurality of memory means, each of the memory means comprising a plurality of dynamic memory cells arrayed in a matrix of rows and columns, a row of memory cells comprising a word line;
• address means for receiving row address, column address, and memory cell array address signals;
• row address decoder means responsive to row address signals for generating a selected address indicative of a word line of a memory array where data is to be written into or read out of;
• a plurality of refresh decoder means for activating word lines to be refreshed;
• sense amplifier means, the amplifier means amplifying signals emitted from a word line indicative of data stored in the word line, upon activation of a word line by the refresh decoder means, the amplifier means reading data stored in the word line, amplifying the data, and writing the amplified data into the word line for refreshing the data, the amplifier means enabling data stored in the word line being refreshed to be read out of the device;
• programmable internal oscillation means for generating and adjusting a self-refreshing time period;
• address counting means coupled to the oscillation means for receiving output pulses therefrom to increment the counting means, the counting means generating an internal refreshing address and transmitting a refresh signal to a corresponding one of the refresh decoder means for activating a memory word line corresponding to the refreshing address, the refresh decoder means activating the word line so that the corresponding sense amplifier means refreshes the data stored in the word line, the counting means being continuously incremented, such that once the data stored in a first word line of a first one of the memory cell arrays is refreshed, the internal refreshing address is incremented to a first word line of a second memory cell array, each word line being refreshed during one self-refreshing time period;
• programmable timer means for counting down a write delay time period;
• logic means coupled to the timer means;
• and
• internal comparator means coupled to the address counting means and to the row address decoder means, the comparator comparing an external address to be written, indicated by the row address signal, and the internal refreshing address generated by the counting means, whereby if the comparator means detects that the external address to be written matches the internal address being refreshed, the comparator means transmits a match signal to the logic means to prevent the data from being written, the logic means signaling the timer to begin counting down the write delay time period, the logic means enabling the data to be written to the refreshed address once the write delay has expired, such that a maximum write delay time period is equal to one self-refreshing time period for preventing a substantially long write delay time period and to reduce noise generated by the device when data is refreshed.

A method of internal self-refreshing in a semiconductor memory device, the method comprising the steps of:

• providing a plurality of memory cell arrays, each array comprising a matrix of rows and columns, a row of memory cells comprising a word line, each memory cell comprising a single transistor;
• providing a plurality of address terminals for receiving row address, column address, and memory array address signals, respectively;
• providing a plurality of row address decoders responsive to row address signals for generating a selected address indicative of a word line of a memory array where data is to be written into or read out of;
• providing a plurality of refresh decoders for activating a word line to be refreshed, one refresh decoder for each memory cell array;
• providing a plurality of sense amplifiers, one amplifier coupled to each memory cell array, the amplifier amplifying a signal emitted from each memory cell in a word line indicative is of data stored in the cell, upon activation of the word line by the refresh decoder, the amplifier reading data stored in the word line, amplifying the data, and writing the amplified data into the word line for refreshing the data, the amplifier enabling data stored in the word line being refreshed to be read out of the device;
• providing an internal clock generator for generating and adjusting a self-refreshing time period;
• providing an address counter for receiving output pulses from the clock generator for incrementing the counter, the counter generating an internal refreshing address and transmitting a refresh signal to a corresponding one of the refresh decoders for activating a memory word line corresponding to the refreshing address, the refresh decoders activating the word line so that the corresponding sense amplifier refreshes the data stored in the word line, the counter refreshing the memory cell arrays using a refresh process comprising the steps of;
• (a) incrementing the internal refreshing address to a first word line in a first memory cell array corresponding to the internal refreshing address,
• (b) signaling a corresponding refresh decoder for activating the word line,
• (c) upon activation of the word line by the refresh decoder, the amplifier reading data stored in the word line, amplifying the data, and writing the amplified data into the word line for refreshing the data stored in the word line,
• (d) incrementing the refreshing address to a first word line in a second memory cell array,
• (e) repeating steps (b) and (c),
• (f) continuously incrementing the internal refreshing address until data stored in the first word line in each of the memory cell arrays, of the plurality of memory cell arrays, is refreshed,
• (g) incrementing the refreshing address to a second word line in the first memory cell array,
• (h) repeating steps (b) and (c),
• (i) incrementing the refreshing address to a second word line in the second memory cell array,
• (j) continuously incrementing the internal refreshing address until a last word line in a last one of the memory cell arrays is refreshed,
• (k) incrementing the refreshing address to the first word line in the first memory cell array,
• (l) repeating steps (b) and (c), such that the counter continuously increments the refreshing address for continuously refreshing data stored in each word line of each memory cell array, each word line being refreshed during one self-refreshing time period;
• providing a programmable timer for counting down a write delay time period;
• providing control logic coupled to the timer;
• and
• providing a comparator coupled to the address counter and to row address and memory address terminals, the comparator comparing an external address to be written, indicated by the row address signal, and the internal refreshing address generated by the counter, whereby if the comparator detects that the external address to be written matches the internal address being refreshed, the comparator transmits a match signal to the control logic to prevent the data from being written, the control logic signaling the timer to begin counting down the write delay time period, the control logic enables the data to be written to the refreshed address once the write delay has expired, such that a maximum write delay time period is equal to one self-refreshing time period for preventing a substantially long write delay time period and to reduce noise generated by the device when data is refreshed.