Ring oscillator using even numbers of differential stages with current mirrors

A ring oscillator comprising:

• an even number of differential stages connected in tandem to form a ring configuration, each of said stages including a pair of semiconductor devices connected in a differential pair configuration with a common connection, a current sink being connected to said common connection, and two current sources, each one of said two current sources being connected to deliver current to a different one of said semiconductor devices;
• a controller circuit for setting a value of current in said current sink and said two current sources, said controller circuit including a primary leg of a first current mirror having a current of I;
• said current sink of each stage being connected as a secondary leg of said first current mirror;
• characterized in that said controller circuit includes a primary leg of a second current mirror, said current sources being connected as secondary legs of said second current mirror, and said first current mirror includes an additional secondary leg connected as a source of current of (1+.varies.)I for said primary leg of said second current mirror, where .varies. is a number greater than zero.

A ring oscillator comprising a plurality of differential stages each one of which having first and second inputs and outputs, said stages being connected in tandem with inputs connected to outputs in order to form a ring configuration, each of said stages including two current sources and a current sink each of which having a bias input for receiving a bias potential that determines a value of its respective current;

• and a bias control circuit for providing a first bias potential to the bias input for said current sources in all of said stages and a second bias potential to the bias input for said current sinks in all of said stages;
• characterized in that said bias control circuit includes a first pair of semiconductor MOSFETs connected in a cascode arrangement with the source of one of said pair connected to the drain of the other of said pair to create a first junction, a circuit for providing a current of I into said cascoded first pair of MOSFETs, said second bias potential being derived from said first junction, a second pair of MOSFETs connected in a cascode arrangement to form a second junction, said second junction being directly connected to said first junction, said second pair of MOSFETs each having a channel width to length (W/L) ratio that is larger by a factor of (1+.varies.) than the channel W/L ratio of said first pair of MOSFETs, where .varies. is a number greater than zero, and a circuit responsive to a current in said cascoded second pair of MOSFETs for providing said first bias potential to the current sources in all of said stages.

A ring oscillator comprising a plurality of stages each of which having first and second inputs and outputs, said stages being connected in tandem to form a ring configuration, each of said stages including a differential amplifier having a first and second MOSFETs of a particular polarity channel type, said first and second MOSFETs each having a source, drain and gate, the sources of said first and second MOSFETs being connected together to form a common connection, said gates of said first and second MOSFETs serving as the first and second respective inputs of the stage represented by said differential amplifier, and the drains of said first and second MOSFETs serving as respective outputs of the stage represented by said differential amplifier, first and second current sources connected respectively to the drains of said first and second MOSFETs, a current sink connected to said common connection;

• and a controlling circuit for controlling a value of current in said first and second current sources and current sink in all of said stages;
• characterized in that said controlling circuit includes a primary leg of a first current mirror having a current of I in response to an external control potential, the current sink in each of said stages being connected as a secondary leg of said first current mirror;
• an additional secondary leg of said first current mirror having a current of (1+.varies.)I, where .varies. is a number greater than zero;
• and a primary leg of a second current mirror connected to receive the current of (1+.varies.)I from said additional secondary leg of said first current mirror, the current sources in each of said stages being connected as secondary legs of said second current mirror.