Logic gate with controllable hysteresis and high frequency voltage controlled oscillator

A circuit having an input lead and an output lead, said circuit comprising:

• a first logic section having an input lead connected to said input lead of said circuit, an output lead, a first supply voltage lead, and a second supply voltage lead, said first logic section comprising a first complementary symmetry inverter;
• a second logic section having an input lead, an output lead connected to said output lead of said circuit, a first supply voltage lead, and a second supply voltage lead, said second logic section comprising a second complementary symmetry inverter, said input lead of said second logic section coupled to said output lead of said first logic section;
• and
• a hysteresis control section having a first lead, a second lead, a third lead and a supply voltage lead, said first lead coupled to said output lead of said first logic section, said second lead coupled to said output lead of said second logic section, said third lead coupled to said input lead of said first logic section, said hysteresis control section comprising:
• a first P-channel field effect transistor having a gate, a source and a drain, said gate of said first P-channel field effect transistor being coupled to said input lead of said first logic section, said drain of said first P-channel field effect transistor being coupled to said input lead of said second logic section;
• a second P-channel field effect transistor having a gate, a source and a drain, said gate of said second P-channel field effect transistor being coupled to said output lead of said second logic section, said drain of said second P-channel field effect transistor being coupled to said source of said first P-channel field effect transistor, said source of said second P-channel field effect transistor being coupled to said first supply voltage lead of said second logic section;
• a first N-channel field effect transistor having a gate, a source and a drain, said gate of said first N-channel field effect transistor being coupled to said input lead of said first logic section, said drain of said first N-channel field effect transistor being coupled to said input lead of said second logic section;
• and
• a second N-channel field effect transistor having a gate, a source and a drain, said gate of said second N-channel field effect transistor being coupled to said output lead of said second logic section, said drain of said second N-channel field effect transistor being coupled to said source of said first N-channel field effect transistor, said source of said second N-channel field effect transistor being coupled to said second supply voltage lead of said second logic section.