Oscillator for generating a varying amplitude feed forward PFC modulation ramp

An oscillator for generating a clock output signal and a varying amplitude ramp output signal for use within a power factor correction circuit, comprising:

• a. a clock output signal generating circuit for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state, wherein the clock output signal is at the first output state at a beginning of the period and at the second output state at an end of the period and wherein the clock output signal generating circuit comprises a second timing resistor, a second timing capacitor and a second discharge transistor and further wherein the clock output signal is coupled for controlling the second discharge transistor;
• b. a ramp output signal generating circuit including a first timing resistor, a first timing capacitor and a first discharge transistor, for generating a varying amplitude ramp output signal having an increasing state and a decreasing state;
• and
• c. a synchronizing circuit coupled to receive the clock output signal from the clock output signal generating circuit and for controlling the first discharge transistor for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal also has the frequency and the corresponding period, and further wherein a synchronizing output has a duty cycle equal to a predetermined percentage of the period.

An oscillator for generating a clock output signal and a varying amplitude ramp output signal for use within a power factor correction circuit, comprising:

• a. a first timing resistor having a first terminal and a second terminal, the first terminal of the first timing resistor coupled to a power supply;
• b. a first timing capacitor having a first terminal and a second terminal, the first terminal of the first timing capacitor coupled to the second terminal of the first timing resistor forming a timing ramp node and the second terminal of the first timing capacitor coupled to a ground;
• c. a voltage divider network including a first resistor, a second resistor and a third resistor each having a first terminal and a second terminal, the first terminal of the first resistor coupled to the power supply, the second terminal of the first resistor coupled to the first terminal of the second resistor forming a high threshold node, the second terminal of the second resistor coupled to the first terminal of the third resistor forming a low threshold voltage node and the second terminal of the third resistor coupled to the ground;
• d. a first discharge resistor having a first terminal and a second terminal, the first terminal of the first discharge resistor coupled to the timing ramp node;
• e. a first discharge transistor having a base, a collector and an emitter, the collector of the first discharge transistor coupled to the second terminal of the first discharge resistor and the emitter of the first discharge transistor coupled to the ground;
• f. a first comparator having a negative input, a positive input and an output, the negative input of the first comparator coupled to the high threshold node and the positive input of the first comparator coupled to the timing ramp node;
• g. a second comparator having a negative input, a positive input and an output, the negative input of the second comparator coupled to the timing ramp node and the positive input of the second comparator coupled to the low threshold node;
• h. a flip flop having an S input, an R input and a Q output, the S input coupled to the output of the first comparator, the R input coupled to the output of the second comparator and the Q output coupled to the base of the first discharge transistor thereby forming a clock output signal node;
• i. a voltage rectifier circuit having an input coupled to receive an alternating current voltage signal and an output producing a full wave rectified signal output;
• j. a second timing resistor having a first terminal and a second terminal, the first terminal of the second timing resistor coupled to the full wave rectified signal output;
• k. a second timing capacitor having a first terminal and a second terminal, the first terminal of the second timing capacitor coupled to the second terminal of the second timing resistor and the second terminal of the second timing capacitor coupled to the ground;
• l. a second discharge resistor having a first terminal and a second terminal, the first terminal of the second discharge resistor coupled to the second terminal of the second timing resistor and to the first terminal of the second timing capacitor thereby forming a varying amplitude ramp signal output node;
• m. a second discharge transistor having a base, a collector and an emitter, the collector of the second discharge transistor coupled to the second terminal of the second discharge resistor and the emitter of the second discharge transistor coupled to the ground;
• n. a one-shot circuit having an input and an output, the input of the one-shot circuit coupled to the clock output signal node and the output of the one-shot circuit coupled to the base of the second discharge transistor, wherein the one-shot circuit outputs a synchronizing output signal having a duty cycle equal to a predetermined percentage of a period of the clock output signal.

An oscillator, comprising:

• a. means for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state wherein at a beginning of the period the clock output signal is at the first output state and at an end of the period the clock output signal is at the second output state;
• b. means for generating a varying amplitude ramp output signal having an increasing state and a decreasing state wherein the ramp output signal is coupled for controlling a switch of a power factor correction circuit;
• and
• c. means for synchronizing coupled to the means for generating a clock output signal and to the means for generating a varying amplitude ramp output signal for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal is generated with the frequency and the corresponding period.

An oscillator for generating a clock output signal and a varying amplitude ramp output signal, comprising:

• a. a clock output signal generating circuit for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state, wherein the clock output signal is at the first output state at a beginning of the period and at the second output state at an end of the period;
• b. a ramp output signal generating circuit including a first timing resistor, a first timing capacitor and a first discharge transistor, for generating a varying amplitude ramp output signal having an increasing state and a decreasing state wherein the ramp output signal is coupled for controlling a switch of a power factor correction circuit;
• and
• c. a synchronizing circuit coupled to receive the clock output signal from the clock output signal generating circuit and for controlling the first discharge transistor for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal also has the frequency and the corresponding period, and further wherein a synchronizing output has a duty cycle equal to a predetermined percentage of the period.

A synchronizing circuit for synchronizing a first output signal, having a first state, a second state, a first frequency and a first corresponding period, generated by a first output signal generating circuit, with a second output signal, having a second frequency and a second corresponding period, generated by a second output signal generating circuit, so that the first output signal and the second output signal have an equal frequency and corresponding period, wherein the first output signal is a clock signal and the second output signal is a varying ramp output signal, the synchronizing circuit comprising:

• a. means for receiving the first output signal;
• b. means for transmitting a control output signal having a duty cycle coupled to the means for receiving and to the second output signal generating circuit for controlling the second frequency so that the second frequency is equal to the first frequency, wherein the duty cycle is equal to a predetermined percentage of the first corresponding period;
• and
• c. means for comparing the second output signal to an error signal for forming a switch control signal, wherein the error signal is representative of a difference between a power factor correction circuit output voltage and a desired output voltage and wherein the switch control signal is coupled to control a switch of the power factor correction circuit.