Semiconductor integrated circuit device having power reduction mechanism

A semiconductor integrated circuit device, comprising:

• a logic gate having a series connection of at least a source/drain path of a first MOS transistor and a source/drain path of a second MOS transistor between a first node and a second node and further connected to provide an output signal from a common terminal of the connection;
• control means connected to receive a control signal, said control means being provided at least either between said first node and a first potential point or between said second node and a second potential point, wherein
• said control means permits a comparatively large current to flow in said logic gate in response to said control signal being in a first state;
• said control means limits the current flowing in said logic gate to a current smaller than said comparatively large current in response to said control signal being set to a second state different from said first state wherein the source/drain path of said first MOS transistor is between said first node and the common terminal of the connection and the source/drain path of said second MOS transistor is between said second node and the common terminal of the connection;
• and
• a plurality of said logic gates, wherein an output of one said logic gate at a preceding stage is connected to an input of another said logic gate at a latter stage in consecutive order, thereby to form a logic gate chain further a plurality of said control means, said plurality of control means being structured so that a voltage swing of an output of a logic gate at a latter stage becomes smaller successively than the voltage swing of the output of logic gate at a preceding stage in said logic gate chain when said control signal is in said second state.

A semiconductor integrated circuit device comprising:

• at least one logic circuit;
• means for cutting off an operating current of said logic circuit;
• means for holding the logic state of said logic circuit, whose input and output are connected to the output of said logic gate, wherein:
• the output of said logic circuit is held by said means for holding the output at least while the leakage current of said logic circuit is cut off by said means for cutting off the operating current;
• and
• wherein said holding means has a MOS transistor whose channel width is smaller than that of a MOS transistor of said logic circuit.

A device for controlling operation of an electronic apparatus between at least two operating states, said electronic apparatus having a central processing unit and a plurality of other units, with a semiconductor integrated device in accordance with data sent from said central processing unit, comprising:

• a logic gate having a series connection of at least a source/drain path of a first MOS transistor and a source/drain pat of a second MOS transistor between a first node and a second node and further connected to provide an output signal from a common terminal of the connection;
• control means connected to receive a control signal, said control means being provided at least either between said first node and a first potential point or between said second node and a second potential point, wherein;
• said control means permits a comparatively large current to flow in said logic gate in response to said control signal being in a first state;
• and
• said control means limits the current flowing in said logic gate to a current smaller than said comparatively large current in response to said control signal being set to a second state different from said first state wherein the source/drain path of said first MOS transistor is between said first node and the common terminal of the connection and the source/drain path of said second MOS transistor is between said second node and the common terminal of the connection;
• wherein said control means is formed of a first current supply means for supplying said comparatively large current and a second current supply means for supplying said small current connected in parallel with each other;
• said first current supply means is composed of at least a third MOS transistor whose source/drain is connected either between said first node and said first potential point or between said second node and said second potential point;
• and
• wherein a threshold voltage of said third MOS transistor is greater than the threshold voltage of said first or second MOS transistor when said third transistor is n-type, and wherein a threshold voltage of said third MOS transistor is less than the threshold voltage of said first or second MOS transistor when said third transistor is p-type.

A semiconductor integrated circuit device comprising:

• at least one logic circuit;
• means for cutting off an operating current of said logic circuit;
• means for holding the logic state of said logic circuit, whose input and output are connected to the output of said logic gate, wherein:
• the output of said logic circuit is held by said means for holding the output at least while the leakage current of said logic circuit is cut off by said means for cutting off the operating current;
• and
• wherein said holding means has a MOS transistor whose threshold voltage is larger in absolute value than that of a MOS transistor of said logic circuit.

A semiconductor integrated circuit device, comprising:

• a first potential point for supplying a first potential;
• a second potential point for supplying a second potential;
• a logic gate provided with at least a first MOS transistor and a second MOS transistor connected in series with each other between a first node and a second node, supplied with a potential from said first potential point and said second potential point through said first node and said second node, and outputting a logic output signal from a common terminal of said first MOS transistor and said second MOS transistor;
• control means connected between said first potential point and said first node and/or between said second potential point and said second node for controlling a current flowing between said first node and said second node between a first current value which makes logic switching operation of said logic gate possible and a second current value smaller than the first current value required for logic standby operation of said logic gate depending on the necessity of logic switching operation;
• wherein said first MOS transistor and said second MOS transistor have different channel type from each other, and said logic gate is a CMOS logic gate;
• voltage holding means whose input and output are connected to an output of said logic gate for holding a voltage of a logic output signal of said logic gate when said current flowing between said first node and said second node shows said second current value;
• wherein said holding means has a MOS transistor whose channel width is smaller than that of said first or second MOS transistor.

A semiconductor integrated circuit device, comprising:

• a first potential point for supplying a first potential;
• a second potential point for supplying a second potential;
• a logic gate provided with at least a first MOS transistor and a second MOS transistor connected in series with each other between a first node and a second node, supplied with a potential from said first potential point and said second potential point through said first node and said second node, and outputting a logic output signal from a common terminal of said first MOS transistor and said second MOS transistor;
• control means connected between said first potential point and said first node and/or between said second potential point and said second node for controlling a current flowing between said first node and said second node between a first current value which makes logic switching operation of said logic gate possible and a second current value smaller than the first current value required for logic standby operation of said logic gate depending on the necessity of logic switching operation;
• wherein said first MOS transistor and said second MOS transistor have different channel type from each other, and said logic gate is a CMOS logic gate;
• voltage holding means whose input and output are connected to an output of said logic gate for holding a voltage of a logic output signal of said logic gate when said current flowing between said first node and said second node shows said second current value;
• wherein said holding means has a MOS transistor whose threshold voltage is larger in absolute value than that of said first or second MOS transistor.

A semiconductor integrated circuit device, comprising:

• a first potential point for supplying a first potential;
• a second potential point for supplying a second potential;
• a logic gate provided with at least a first MOS transistor and a second MOS transistor connected in series with each other between a first node and a second node, supplied with a potential from said first potential point and said second potential point through said first node and said second node, and outputting a logic output signal from a common terminal of said first MOS transistor and said second MOS transistor;
• control means connected between said first potential point and said first node and/or between said second potential point and said second node for controlling a current flowing between said first node and said second node between a first current value which makes logic switching operation of said logic gate possible and a second current value smaller than the first current value required for logic standby operation of said logic gate depending on the necessity of logic switching operation;
• wherein said first MOS transistor and said second MOS transistor have different channel type from each other, and said logic gate is a CMOS logic gate;
• voltage holding means whose input and output are connected to an output of said logic gate for holding a voltage of a logic output signal of said logic gate when said current flowing between said first node and said second node shows said second current value:
• wherein said control means have a MOS transistor whose threshold voltage is larger in absolute value than that of a MOS transistor of said logic circuit.

A device for controlling operation of an electronic apparatus between at least two operating states, said electronic apparatus having a central processing unit and a plurality of other units, with a semiconductor integrated device in accordance with data sent from said central processing unit, comprising:

• at least one logic circuit;
• means for cutting off an operating current of said logic circuit;
• and
• means for holding the logic state of said logic circuit, whose input and output are connected to the output of said logic state;
• wherein:
• the output of said logic circuit is held by said means for holding the output at least while the leakage current of said logic circuit is cut off by said means for cutting off the operating current;
• wherein said holding means has a MOS transistor whose channel width is smaller than that of a MOS transistor of said logic circuit.

A device for controlling operation of an electronic apparatus between at least two operating states, said electronic apparatus having a central processing unit and a plurality of other units, with a semiconductor integrated device in accordance with data sent from said central processing unit, comprising:

• at least one logic circuit;
• means for cutting off an operating current of said logic circuit;
• and
• means for holding the logic state of said logic circuit, whose input and output are connected to the output of said logic state;
• wherein:
• the output of said logic circuit is held by said means for holding the output at least while the leakage current of said logic circuit is cut off by said means for cutting off the operating current;
• wherein said holding means has a MOS transistor whose threshold voltage is larger in absolute value than that of a MOS transistor of said logic circuit.

A device for controlling operation of an electronic apparatus between at least two operating states, said electronic apparatus having a central processing unit and a plurality of other units, with a semiconductor integrated device in accordance with data sent from said central processing unit, comprising:

• at least one logic circuit;
• means for cutting off an operating current of said logic circuit;
• and
• means for holding the logic state of said logic circuit, whose input and output are connected to the output of said logic state;
• wherein:
• the output of said logic circuit is held by said means for holding the output at least while the leakage current of said logic circuit is cut off by said means for cutting off the operating current;
• wherein said cutting off means has a MOS transistor whose threshold voltage is larger in absolute value than that of a MOS transistor of said logic circuit.

A semiconductor integrated circuit device comprising:

• a plurality of logic gates each of which includes a first MOS transistor connected to an output terminal thereof, wherein an output of a logic gate at a preceding stage is connected to an input of a logic gate at a latter stage in consecutive order, thereby to form a logic gate chain;
• cutting off means for cutting off a leakage current of said logic gate chain;
• and
• output holding means connected to an output terminal of said logic gate chain for holding the output of said logic gate chain at least while the leakage current of said logic gate chain is cut off by said cutting off means;
• wherein said cutting off means includes a second MOS transistor, whose channel width is smaller than the total value of the channel widths of said first MOS transistors of said plurality of logic gates.