US 5,576,557 AGranted

Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits

AssigneeUnited Microelectronics Corp.

InventorsMing-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Chung-Yuan Lee, Joe Ko

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Abstract

An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.

Claims14

Dependent claims

A circuit arrangement for electrostatic discharge protection of a semiconductor integrated circuit (IC) device, one said circuit being located between each I/O buffering pad that connects to one lead pin with internal circuitry of said IC, said circuit arrangement being connected to both of a pair of power terminals and a conductor connecting said I/O buffering pad and said internal circuitry, said circuit arrangement comprising:

a first SCR having an anode, a cathode, an anode gate and a cathode gate, said anode and anode gate of said first SCR being connected to the first of said pair of power terminals, said cathode of said first SCR being connected to its associated buffering pad, and said cathode gate of said first SCR being connected to the second of said pair of power terminals;
a PMOS transistor having drain, source, gate, and bulk terminals, said gate, source and bulk terminals of said PMOS transistor being connected to the first of said pair of power terminals, said drain terminal of said PMOS transistor being connected to said cathode gate of said first SCR;
a second SCR having an anode, a cathode, an anode gate and a cathode gate, said cathode and cathode gate of said second SCR being connected to the second of said pair of power terminals, said anode of said second SCR being connected to its associated I/O buffering pad, and said anode gate of said second SCR being connected to the first of said pair of power terminals;
and
an NMOS transistor having drain, source, gate, and bulk terminals, said gate, source and bulk terminals of said NMOS transistor being connected to the second of said pair of power terminals, said drain terminal of said NMOS transistor being connected to said anode gate of said second SCR.

2 more elements

Dependencies are inferred from the claim text.