Low noise tri-state output buffer

A buffer circuit, comprising

• a first pair of tristate input translators connected in parallel to an input of the circuit, each input translator being characterized by a ramp rate for a signal transition that is at most two times higher at its output than at its input,
• a first set of pull-up and pull-down output. transistors connected in series between first and second voltage supply lines with an output node formed between said pull-up and pull-down output transistors, said input translators driving respective control gates of said pull-up and pull-down output transistors,
• wherein said input translator that drives said pull-up transistor of said first set of output transistors has an input transition voltage that is lower than a nominal transition voltage of the circuit and said input translator that drives said pull-down transistor of said first set of output transistors has a different input transition voltage that is higher than said nominal transition voltage, said nominal transition voltage being between voltage levels of said first and second voltage supply lines and between predefined logic low and logic high voltage levels for input signals received at said input of the circuit,
• a second set of pull-up and pull-down output transistors connected in series between said first and second voltage supply lines in parallel with said first set of pull-up and pull-down output transistors with said output node also connected between said pull-up and pull-down output transistors of said second set,
• a second pair of tristate input translators connected in parallel with each other and with said first pair of tristate input translators to said input of the circuit, each of said second pair of input translators also being characterized by a ramp rate for a signal transition that is at most two times higher at its output than at its input, said second pair of tristate input translators driving respective control gates of said second set of pull-up and pull-down output transistors, and
• means responsive to a voltage level of said output node and connected to said control gates of said second set of pull-up and pull-down output transistors for shutting off said pull-up transistor of said second set during a low-to-high transition when said output node has exceeded a first voltage level and shutting off said pull-down transistor of said second set during a high-to-low transition when said output node has fallen below a second voltage level, said first and second voltage levels both being between voltage levels of said first and second voltage supply lines.

A buffer circuit, comprising

• first and second pull-up output transistors connected in parallel between a first voltage supply line and an output node,
• first and second pull-down output transistors connected in parallel between a second voltage supply line and said output node,
• first, second, third and fourth tristate input translators with inputs connected in common to an input terminal of the circuit and with outputs respectively driving said first and second pull-up and first and second pull-down output transistors, and
• feedback means connected to said output node for generating first and second control signals when said output node respectively exceeds a logic high transition voltage and falls below a logic low transition voltage, said first control signal being coupled to a tristate input of said second input translator driving said second pull-up output transistor, said second control signal being coupled to a tristate input of said fourth input translator driving said second pull-down output transistor.