Method for fabricating a stacked capacitor with a self aligned node contact in a memory cell

A method of fabricating a capacitor of a semiconductor memory device on a substrate, said substrate having a field oxide region with a word line formed thereon, said substrate having a MOS transistor formed thereon, said transistor having a gate, a source region and a drain region, said word line and said gate having silicon nitride sidewall spacers, and the method comprising the steps of:

• a) forming a first planar insulation layer over said substrate, said first planar insulation layer formed of silicon oxide;
• b) sequentially forming a first conductive layer and a second insulation layer over the first insulation layer, said first conductive layer formed of polysilicon and said second insulation layer formed of silicon oxide;
• c) forming a first opening in said second insulation layer over said source region and exposing said first conductive layer, said first opening defined by vertical sidewalls of said second insulating layer;
• d) depositing a polysilicon layer over said second insulation layer;
• e) anisotropically etching said polysilicon layer and said first conductive layer to expose said second insulation layer thereby forming first sidewall spacers on said vertical sidewalls of said second insulation layer, said first sidewall spacers forming a second opening;
• f) anisotropically etching said first conductive layer and said first insulation layer through said second opening, and using said silicon nitride sidewall spacers as a mask thereby exposing said source region, said anisotropic etch forming a node contact opening;
• g) removing said second insulating layer exposing portions said first conductive layer;
• h) forming a bottom storage electrode over the exposed portions of said first conductive layer and said first sidewall spacers, and in said node contact opening;
• i) depositing a capacitor dielectric layer covering said bottom storage electrode;
• j) forming a top plate electrode over said capacitor dielectric layer;
• and
• forming a top insulation layer and a metal layer over a substrate surface.

A method of fabricating DRAM having a capacitor on a semiconductor substrate, comprising the steps of:

• a) providing a MOS (metal oxide semiconductor) transistor having a gate centered between spaced source and drain region, and providing a word line over a field oxide region, said gate and said word line having silicon nitride sidewall spacers,
• b) forming a first insulation layer composed of silicon oxide over said transistor, said word line, and said field oxide region;
• c) sequentially forming a first conductive layer and a second insulation layer over said first insulation layer, said first conductive layer composed of polysilicon and said second insulation layer composed of silicon oxide;
• d) forming a first opening in said second insulation layer centered over said source region and exposing said first conductive layer, said first opening defined by vertical sidewalls of said second insulation layer;
• e) depositing a polysilicon layer over the said second insulation layer;
• f) anisotropically etching said polysilicon layer and said first conductive layer to expose said second insulation layer thereby forming first sidewall spacers on said vertical sidewalls of said second insulation layer, said first sidewall spacers forming a second opening;
• g) anisotropically etching portions of said first conductive layer and said first insulation layer through said second opening and said silicon nitride spacers thereby exposing said source region, said anisotropic etch forming a node contact opening;
• h) removing said second insulation layer exposing remaining portions of said first conductive layer;
• i) forming a bottom storage electrode over the exposed portions of said first conductive layer and said first sidewall spacers, and filling said node contact opening, said bottom storage electrode composed of a doped polysilicon layer and a hemispherical grain layer;
• j) depositing a capacitor dielectric layer over said bottom storage electrode;
• k) forming a top plate electrode over said capacitor dielectric layer;
• and
• l) forming a top insulation layer and a metal layer over said top plate electrode and said first insulation layer.