Single-rail self-resetting logic circuitry
AssigneeInternational Business Machines Corporation
InventorsChristopher M. Durham, Visweswara R. Kodali, Salim A. Shah
Life of this patent
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Abstract
A forward single-rail self-resetting reset circuit is utilized to reset a logic circuit to a selected state subsequent to each iteration of a logical operation on inputted data into the logic circuit. The reset circuit receives at least one of the data inputs and its complement signal so that the reset signal produced by the reset circuit is activated regardless of the voltage level of the data input signals.
Claims19
A logic circuit, comprising:
- one or more data inputs to said logic circuit;
- one or more data outputs from said logic circuit;
- and
- a reset circuit coupled to said logic circuit, said reset circuit coupled to said one or more data inputs, said reset circuit coupled to a complement of said one or more data inputs.
A method for precharging a logic circuit to a selected state, wherein said logic circuit has one or more data inputs and a data output, said method comprising the steps of:
- receiving one of said one or more data inputs;
- receiving a complement of said one of said one or more data inputs;
- producing a precharge signal in response to receipt of said one of said one or more data inputs and said complement of said one of said one or more data inputs;
- sending said precharge signal to said logic circuit;
- precharging said logic circuit to said selected state in response to receipt of said precharge signal;
- and
- delaying said precharging step until subsequent to performance of a logical operation by said logic circuit on said one or more data inputs.
A method for precharging a logic circuit to a selected state, wherein said logic circuit has one or more data inputs and a data output, said method comprising the steps of:
- receiving one of said one or more data inputs:
- receiving a complement of said one of said one or more data inputs;
- producing a precharge signal in response to receipt of said one of said one or more data inputs and said complement off said one of said one or more data inputs;
- sending said precharge signal to said logic circuit;
- precharging said logic circuit to said selected state in response to receipt of said precharge signal;
- and
- delaying said precharging step until subsequent to performance of a logical operation by said logic circuit on said one or more data inputs, wherein said step of receiving one of said one or more data inputs further comprises the step of applying said one of said one or more data inputs to a gate electrode of a first FET device, and wherein said step of receiving a complement of said one of said one or more data inputs further comprises the step of applying said complement of said one of said one or more data inputs to a gate electrode of a second FET device, wherein said first and second FET devices are coupled in parallel between a voltage potential and a node within a reset circuit coupled to said logic circuit.
A data processing system comprising a plurality of devices coupled together by a bus, wherein one of said plurality of devices comprises logic circuitry, wherein said plurality of devices includes a processor, a storage device, a random access memory, a display device, and an input device, said logic circuitry comprising:
- a plurality of staged logic circuits;
- means, coupled to a first one of said plurality of staged logic circuits, for receiving a plurality of data input signals;
- a reset circuit coupled to a means for receiving one of said plurality of data input signals;
- means, coupled to said reset circuit, for receiving a complement signal of said one of said plurality of data input signals;
- timing circuits coupled to each of said plurality of staged logic circuits;
- and
- means for coupling an output of said reset circuit to each of said plurality of staged logic circuits through said timing circuits.
Dependencies are inferred from the claim text.