Charge dissipation in capacitively loaded ports

A method for reducing peak transition currents on a capacitively loaded port in a monolithic integrated circuit having an analog-to-digital and digital-to-analog signal conversion module and a digital audio signal synthesizer module, said method comprising the steps of:

• providing a capacitively derived load signal;
• linking said load signal to the integrated circuit ground through plural parallel paths, each path having a gated transistor and a resistor;
• providing plural triggering networks arranged in a sequential cascade;
• generating a digitally selected threshold signal;
• comparing said load signal and said threshold signal to derive a pull-down signal;
• supplying said pull-down signal as an input signal to said cascade;
• clocking said plural triggering networks with a common clocking signal;
• and
• sequentially enabling said plural parallel paths by supplying selected ones of said gated transistors with an output signal from selected corresponding ones of said plural triggering networks, said output signals derived sequentially as the state of said cascade input signal sequentially propagates through said cascade in substantial timed correspondence with said clocking signal.

A method for regulating peak transition currents on a capacitively loaded port, said method comprising the steps of:

• providing a monolithic integrated circuit;
• providing said monolithic integrated circuit with a capacitively derived load signal;
• linking said load signal to the integrated circuit ground through plural parallel paths, each path having a switchable transistor;
• providing plural triggering networks arranged in a sequential cascade, said sequential cascade having an input signal;
• supplying a pull-down signal as said cascade input signal;
• propagating said pull-down signal through said cascade by sequentially activating said plural triggering networks;
• and
• sequentially enabling said plural parallel paths by supplying selected ones of said switchable transistors with an output signal from selected corresponding ones of said sequentially activated plural triggering networks.

A method for regulating peak currents during a HIGH to LOW transition on a capacitively loaded port in a monolithic integrated circuit having an analog-to-digital and digital-to-analog signal conversion module and a digital audio signal synthesizer module, said method comprising the steps of:

• providing a load signal;
• linking said load signal to the integrated circuit ground through first, second, third, and fourth parallel paths, each path characterized by a gated transistor;
• providing first, second, third, and fourth triggering networks, each selected one of said triggering networks having an output signal and an input signal clockable to appear as said output signal of said selected triggering network, said triggering networks arranged in a sequential cascade characterized by said output signal of said first triggering network providing said input signal for said second triggering network and said output signal of said second triggering network providing said input signal for said third triggering network and said output signal of said third triggering network providing said input signal for said fourth triggering network;
• generating a digitally selected threshold signal;
• comparing said load signal and said threshold signal to derive a pull-down signal;
• supplying said pull-down signal as said input signal of said first triggering network of said sequential cascade;
• clocking said first, second, third, and fourth triggering networks with a common clocking signal;
• and
• sequentially enabling said first, second, third, and fourth parallel paths by supplying said gated transistors of said first, second, third, and fourth parallel paths with the corresponding said output signals from said first, second, third, and fourth triggering networks respectively, said output signals derived as said input signal of said first triggering network sequentially propagates through said cascade in substantial correspondence with sequential state changes of said common clocking signal.

A system for regulating peak transition currents on a capacitively loaded port in a monolithic integrated circuit having an analog-to-digital and digital-to-analog signal conversion module and a digital audio signal synthesizer module, said system comprising:

• an input port for receiving a capacitive load signal;
• plural pull-down parallel paths linking said input port and the integrated circuit ground, each path characterized by a gated transistor;
• a digital-to-analog convertor generating a selectable threshold signal;
• a comparator generating a pull-down signal derived from the comparison of said load signal and said selectable threshold signal;
• plural clock responsive triggering networks arranged in a sequential cascade, each selected one of said triggering networks having an output signal supplied to a selected corresponding one of said plural pull-down paths and an input signal clockable to appear as said output signal of said selected triggering network;
• and
• a clocking circuit having a clock-derived signal supplied in substantial coincidence to each of said plural triggering networks to sequentially propagate the state of said pull-down signal through said cascade to sequentially activate said plural pull-down paths.